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Intel(R) 852GME Chipset GMCH and Intel(R) 852PM Chipset MCH
Datasheet
April 2005
Document Number: 253027-004
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 852GME Chipset GMCH & Intel(R) 852PM chipset MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel(R) Pentium(R) 4 processor supporting Hyper-Threading Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/info/hyperthreading/ for more information including details on which processors support Hyper-Threading Technology.
Intel, Pentium, Celeron, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright(c) 2003-2005, Intel Corporation. All rights reserved.
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Contents
1 Overview ........................................................................................................................... 17 1.1 1.2 1.3 Terminology.......................................................................................................... 17 Reference Documents.......................................................................................... 19 System Architecture Overview ............................................................................. 20 1.3.1 Intel(R) 852GME GMCH System Architecture......................................... 20 1.3.2 Intel(R) 852PM MCH System Architecture .............................................. 20 Processor Host Interface...................................................................................... 21 1.4.1 Host Bus Error Checking ...................................................................... 21 Intel(R) 852PM and 852GME DDR SDRAM Interface ............................................ 21 GMCH Internal Graphics Interface....................................................................... 22 1.6.1 GMCH Analog Display Port .................................................................. 23 1.6.2 GMCH Integrated LVDS Port................................................................ 23 1.6.3 GMCH Integrated DVO Port ................................................................. 23 External AGP Graphics Interface ......................................................................... 23 1.7.1 Intel(R) 852PM MCH and Intel(R) 852GME GMCH AGP Interface ............ 23 Hub Interface ........................................................................................................ 24 Address Decode Policies ..................................................................................... 24 Platform Clocking ................................................................................................. 24 System Interrupts ................................................................................................. 25
1.4 1.5 1.6
1.7 1.8 1.9 1.10 1.11 2
Signal Description ............................................................................................................. 27 2.1 2.2 2.3 Host Interface Signals .......................................................................................... 28 DDR SDRAM Interface......................................................................................... 31 AGP Interface Signals .......................................................................................... 33 2.3.1 AGP Addressing Signals ...................................................................... 33 2.3.2 AGP Flow Control Signals .................................................................... 34 2.3.3 AGP Status Signals .............................................................................. 35 2.3.4 AGP Strobes ......................................................................................... 36 2.3.5 AGP/PCI Signals-Semantics ................................................................ 37 Hub Interface Signals ........................................................................................... 39 Clocks................................................................................................................... 40 GMCH Internal Graphics Display Signals ............................................................ 42 2.6.1 Dedicated LVDS Panel Interface .......................................................... 42 2.6.2 Digital Video Port B (DVOB) ................................................................. 43 2.6.3 Digital Video Port C (DVOC)................................................................. 44 2.6.4 GMCH DVO & I2C to AGP Pin Mapping ............................................... 46 2.6.5 Analog Display ...................................................................................... 47 2.6.6 Graphics General Purpose Input/Output Signals ................................. 48 Power Sequencing Signal Description ................................................................. 49 Voltage References, PLL Power .......................................................................... 50 Reset States and Pull-up/Pull-downs................................................................... 52 2.9.1 Full and Warm Reset State................................................................... 53
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Register Description.......................................................................................................... 63 3.1 3.2 3.3 3.4 Conceptual Overview of the Platform Configuration Structure ............................ 63 Nomenclature for Access Attributes..................................................................... 64 Standard PCI Bus Configuration Mechanism....................................................... 65 Routing Configuration Accesses .......................................................................... 65 3.4.1 PCI Bus #0 Configuration Mechanism.................................................. 65 3.4.2 Primary PCI and Downstream Configuration Mechanism .................... 66 3.4.3 AGP/PCI_B Bus Configuration Mechanism.......................................... 66 Register Definitions .............................................................................................. 67 I/O Mapped Registers .......................................................................................... 68 3.6.1 CONFIG_ADDRESS - Configuration Address Register ...................... 68 3.6.2 CONFIG_DATA - Configuration Data Register ................................... 70 Host-Hub Interface Bridge Device Registers (Device #0, Function #0)............... 71 3.7.1 VID - Vendor Identification Register (Device #0) ................................. 73 3.7.2 DID - Device Identification Register (Device #0) ................................. 73 3.7.3 PCICMD - PCI Command Register (Device #0) .................................. 74 3.7.4 PCI Status Register (Device #0)........................................................... 75 3.7.5 RID - Revision Identification (Device #0) ............................................. 76 3.7.6 SUBC - Sub Class Code Register (Device #0).................................... 76 3.7.7 BCC - Base Class Code Register (Device #0) .................................... 77 3.7.8 HDR - Header Type Register (Device #0) ........................................... 77 3.7.9 APBASE - Aperture Base Configuration (Device #0) .......................... 78 3.7.10 SVID - Subsystem Vendor Identification Register (Device #0)............ 79 3.7.11 SID - Subsystem Identification Register (Device #0)........................... 79 3.7.12 CAPPTR - Capabilities Pointer Register (Device #0) .......................... 79 3.7.13 CAPIDCapability Identification Register (Device #0) ........................ 80 3.7.14 RRBAR - Register Range Base Address Register (Device #0) .......... 81 3.7.15 GMC - GMCH Miscellaneous Control Register (Device #0)................ 82 3.7.16 GGC - GMCH Graphics Control Register (Device 0) .......................... 83 3.7.17 DAFC - Device and Function Control Register (Device 0) .................. 84 3.7.18 FDHC - Fixed DRAM Hole Control Register (Device #0) .................... 85 3.7.19 PAM(6:0) - Programmable Attribute Map Register (Device #0) .......... 85 3.7.20 SMRAM - System Management RAM Control Register (Device #0) .. 90 3.7.21 ESMRAMC - Extended System Management RAM Control (Device #0)............................................................................................ 91 3.7.22 ERRSTS - Error Status Register (Device #0) ...................................... 92 3.7.23 ERRCMD - Error Command Register (Device #0) .............................. 93 3.7.24 SMICMD - SMI Error Command Register (Device #0) ........................ 94 3.7.25 SCICMD - SCI Error Command Register (Device #0)......................... 95 3.7.26 SHIC - Secondary Host Interface Control Register (Device #0) .......... 96 3.7.27 ACAPID - AGP Capability Identifier Register (Device #0) ................... 96 3.7.28 AGPSTAT - AGP Status Register (Device #0) .................................... 97 3.7.29 AGPCMD - AGP Command Register (Device #0)............................... 98 3.7.30 AGPCTRL - AGP Control Register (Device #0) .................................. 99 3.7.31 AFT - AGP Functional Register (Device #0)........................................ 99 3.7.32 APSIZE - Aperture Size (Device #0).................................................. 100 3.7.33 ATTBASE - Aperture Translation Table Base Register (Device #0) . 101 3.7.34 AMTT - AGP Interface Multi-Transaction Timer Register (Device #0).......................................................................................... 102 3.7.35 LPTT - Low Priority Transaction Timer Register (Device #0) ............ 103 Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)104
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VID - Vendor Identification Register (Device #0, Function #1) .......... 105 DID - Device Identification Register (Device #0, Function #1) .......... 105 PCICMD - PCI Command Register (Device #0, Function #1) ........... 106 PCISTS - PCI Status Register (Device #0, Function #1)................... 107 RID - Revision Identification Register (Device #0, Function #1) ....... 108 SUBC - Sub-Class Code Register (Device #0, Function #1) ............ 108 BCC - Base Class Code Register (Device #0, Function #1) ............. 108 HDR - Header Type Register (Device #0, Function #1) .................... 109 SVID - Subsystem Vendor Identification Register (Device #0, Function #1) ....................................................................................................... 109 3.8.10 SID - Subsystem Identification Register (Device #0, Function #1).... 109 3.8.11 CAPPTR - Capabilities Pointer Register (Device #0, Function #1) ... 110 3.8.12 DRB - DRAM Row (0:3) Boundary Register (Device #0, Function #1) ........................................................................................ 110 3.8.13 DRA - DRAM Row Attribute Register (Device #0, Function #1) ........ 111 3.8.14 DRT - DRAM Timing Register (Device #0, Function #1) ................... 112 3.8.15 PWRMG - DRAM Controller Power Management Control Register (Device #0, Function #1)..................................................................... 116 3.8.16 DRC - DRAM Controller Mode Register (Device #0, Function #1).... 118 3.8.17 DTC - DRAM Throttling Control Register (Device #0, Function #1) .. 122 Configuration Process Registers (Device #0, Function #3) ............................... 126 3.9.1 VID - Vendor Identification Register (Device #0) ............................... 127 3.9.2 DID - Device Identification Register (Device #0) ............................... 127 3.9.3 PCICMD - PCI Command Register (Device #0) ................................ 128 3.9.4 PCISTS - PCI Status Register (Device #0)........................................ 129 3.9.5 RID - Revision Identification Register (Device #0) ............................ 130 3.9.6 SUBC - Sub-Class Code Register (Device #0) ................................. 130 3.9.7 BCC - Base Class Code Register (Device #0) .................................. 130 3.9.8 HDR - Header Type Register (Device #0) ......................................... 131 3.9.9 SVID - Subsystem Vendor Identification Register (Device #0).......... 131 3.9.10 ID - Subsystem Identification Register (Device #0) ........................... 131 3.9.11 CAPPTR - Capabilities Pointer Register (Device #0) ........................ 132 3.9.12 STRAP - Strap Status (Device #0)..................................................... 132 3.9.13 HPLLCC - HPLL Clock Control Register (Device #0)........................ 133 PCI to AGP Configuration Registers (Device #1, Function #0) ......................... 134 3.10.1 VID1 - Vendor Identification (Device #1) ............................................ 135 3.10.2 DID1 - Device Identification (Device #1)............................................. 135 3.10.3 PCICMD1 - PCI Command Register (Device #1)............................... 136 3.10.4 PCISTS1 - PCI Status Register (Device #1) ...................................... 137 3.10.5 RID - Revision Identification (Device #1)............................................ 137 3.10.6 SUBC1 - Sub-Class Code (Device #1)............................................... 138 3.10.7 BCC1 - Base Class Code (Device #1)................................................ 138 3.10.8 HDR1 - Header Type (Device #1) ...................................................... 138 3.10.9 PBUSN1 - Primary Bus Number (Device #1) ..................................... 139 3.10.10 SBUSN1 - Secondary Bus Number (Device #1) ................................ 139 3.10.11 SUBUSN1 - Subordinate Bus Number (Device #1) ........................... 140 3.10.12 SMLT1 - Secondary Bus Master Latency Timer (Device #1) ............. 140 3.10.13 IOBASE1 - I/O Base Address Register (Device #1)........................... 141 3.10.14 IOLIMIT1 - I/O Limit Address Register (Device #1) ............................ 141 3.10.15 SSTS1 - Secondary Status Register (Device #1)............................... 142 3.10.16 MBASE1 - Memory Base Address Register (Device #1) ................... 143 3.10.17 MLIMIT1 - Memory Limit Address Register (Device #1) .................... 144 3.10.18 PMBASE1 - Prefetchable Memory Base Address Reg (Device #1) .. 145
3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.8.8 3.8.9
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3.10.19 PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1) ... 146 3.10.20 BCTRL - Bridge Control Register (Device #1).................................... 147 3.10.21 ERRCMD1 - Error Command Register (Device #1) ........................... 148 Intel(R) 852GME GMCH Integrated Graphics Device Registers (Device #2, Function #0)........................................................................................................ 149 3.11.1 VID - Vendor Identification Register (Device #2) ............................... 150 3.11.2 DID - Device Identification Register (Device #2) ............................... 150 3.11.3 PCICMD - PCI Command Register (Device #2) ................................ 151 3.11.4 PCISTS - PCI Status Register (Device #2)........................................ 152 3.11.5 RID - Revision Identification Register (Device #2) ............................ 152 3.11.6 CC - Class Code Register (Device #2) .............................................. 153 3.11.7 CLS - Cache Line Size Register (Device #2) .................................... 153 3.11.8 MLT - Master Latency Timer Register (Device #2)............................ 153 3.11.9 HDR - Header Type Register (Device #2) ......................................... 154 3.11.10 GMADR - Graphics Memory Range Address Register (Device #2).. 154 3.11.11 MMADR - Memory Mapped Range Address Register (Device #2) ... 155 3.11.12 IOBAR - I/O Base Address Register (Device #2) .............................. 155 3.11.13 SVID - Subsystem Vendor Identification Register (Device #2).......... 156 3.11.14 SID - Subsystem Identification Register (Device #2)......................... 156 3.11.15 ROMADR - Video BIOS ROM Base Address Registers (Device #2) 156 3.11.16 INTRLINEInterrupt Line Register (Device #2) ................................ 157 3.11.17 INTRPINInterrupt Pin Register (Device #2) .................................... 157 3.11.18 MINGNT - Minimum Grant Register (Device #2) ............................... 157 3.11.19 MAXLAT - Maximum Latency Register (Device #2) .......................... 158 3.11.20 PMCAP - Power Management Capabilities Register (Device #2)..... 158 3.11.21 PMCS - Power Management Control/Status Register (Device #2) ... 159 3.11.22 GCCC GMCH Clock Control Register ........................................... 160 System Memory Address Ranges...................................................................... 161 MS-DOS* Compatibility Area ............................................................................. 163 Extended System Memory Area......................................................................... 165 Main System Memory Address Range (0010_0000h to Top of Main Memory). 166 4.4.1 15 MB - 16 MB Window ..................................................................... 166 4.4.2 Pre-allocated System Memory............................................................ 166 4.4.3 System Management Mode (SMM) Memory Range .......................... 170 4.4.4 System Memory Shadowing ............................................................... 172 4.4.5 I/O Address Space.............................................................................. 172 4.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping............... 173 Host Interface Overview ..................................................................................... 177 Dynamic Bus Inversion....................................................................................... 177 5.2.1 System Bus Interrupt Delivery ............................................................ 177 5.2.2 Upstream Interrupt Messages ............................................................ 178 System Memory Interface .................................................................................. 178 5.3.1 DDR SDRAM Interface Overview ....................................................... 178 5.3.2 Memory Organization and Configuration............................................ 179 5.3.3 DDR SDRAM Performance Description ............................................. 180 5.3.4 Intel(R) 852GME GMCH and Intel(R) 852PM MCH Data Integrity (ECC) 180 Integrated Graphics Overview............................................................................ 180 5.4.1 Intel(R) GMCH 3D/2D Instruction Processing ....................................... 181
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System Address Map ...................................................................................................... 161 4.1 4.2 4.3 4.4
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Functional Description .................................................................................................... 177 5.1 5.2
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5.4.2 3D Engine ........................................................................................... 181 5.4.3 Raster Engine ..................................................................................... 186 5.4.4 GMCH 2D Engine ............................................................................... 189 5.4.5 GMCH Planes and Engines................................................................ 190 5.4.6 Hardware Cursor Plane ...................................................................... 190 5.4.7 Overlay Plane ..................................................................................... 191 5.4.8 Video Functionality.............................................................................. 192 Display Interface................................................................................................. 193 5.5.1 Analog Display Port Characteristics ................................................... 193 5.5.2 Digital Display Interface ...................................................................... 194 AGP Interface Overview..................................................................................... 199 5.6.1 AGP Target Operations ...................................................................... 199 5.6.2 AGP Transaction Ordering ................................................................. 200 5.6.3 AGP Signal Levels .............................................................................. 200 5.6.4 4X AGP Protocol................................................................................. 201 Power and Thermal Management...................................................................... 204 General Description of Supported CPU States .................................................. 205 General Description of ACPI States................................................................... 205 Enhanced Intel SpeedStep(R) Technology Overview ........................................... 206 External Thermal Sensor Input........................................................................... 206
Electrical Characteristics................................................................................................. 209 6.1 6.2 6.3 6.4 6.5 Absolute Maximum Ratings................................................................................ 209 Thermal Characteristics ..................................................................................... 210 Power Characteristics ........................................................................................ 211 Signal Groups..................................................................................................... 213 DC Characteristics ............................................................................................. 216
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Testability ........................................................................................................................ 225 7.1 7.2 7.3 7.4 7.5 XOR Chain Differential Pairs.............................................................................. 225 XOR Chain Exclusion List .................................................................................. 226 XOR Chain Connectivity/Ordering ..................................................................... 227 VCC/VSS Voltage Groups.................................................................................. 238 Power Sequence Recommendation................................................................... 239
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Intel(R) 852GME GMCH and 852PM MCH Strap Pins...................................................... 241 8.1 Strapping Configuration Table............................................................................ 241
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Ballout and Package Information .................................................................................... 243 9.1 Package Mechanical Information ....................................................................... 278
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Figures
Figure 1. Intel(R) 852PM GMCH Chipset System Block Diagram....................................... 13 Figure 2. Intel(R) 852GME GMCH Chipset System Block Diagram .................................... 16 Figure 3 . Full and Warm Reset Waveforms..................................................................... 53 Figure 4. Configuration Address Register......................................................................... 68 Figure 5. Configuration Data Register .............................................................................. 70 Figure 6. PAM Registers ................................................................................................... 87 Figure 7. Simplified View of Intel(R) 852GME GMCH and Intel(R) 852PM MCH System Address Map............................................................................................................ 162 Figure 8. Detailed View of the Intel(R) 852GME GMCH and Intel(R) 852PM MCH System Address Map............................................................................................................ 163 Figure 9. Intel(R) 852GME GMCH Graphics Block Diagram ............................................. 181 Figure 10. LVDS Swing Voltage ..................................................................................... 195 Figure 11. LVDS Clock and Data Relationship............................................................... 196 Figure 12. Panel Power Sequencing .............................................................................. 197 Figure 13. XOR-Tree Chain ............................................................................................ 225 Figure 14. Intel(R) 852GME GMCH Ballout Diagram (Top View)...................................... 243 Figure 15. Intel(R) 852PM MCH Ballout Diagram (Top View) ........................................... 260 Figure 16. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Micro-FCBGA Package Dimensions (Top View)............................................................................................ 278 Figure 17. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Micro-FCBGA Package Dimensions (Side View)........................................................................................... 279
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Tables
Table 1. SDRAM Memory Capacity .................................................................................. 22 Table 2. Intel(R) 852GME GMCH Interface Clocks ............................................................. 25 Table 3. Host Interface Signal Descriptions...................................................................... 28 Table 4. DDR SDRAM Interface Descriptions .................................................................. 31 Table 5. AGP Addressing Signal Descriptions ................................................................. 33 Table 6. AGP Flow Control Signals .................................................................................. 34 Table 7. AGP Status Signal Descriptions ......................................................................... 35 Table 8. AGP Strobe Descriptions .................................................................................... 36 Table 9. AGP/PCI Signals-Semantics Descriptions.......................................................... 37 Table 10. Hub Interface Signals........................................................................................ 39 Table 11. Clock Signals .................................................................................................... 40 Table 12. Dedicated LVDS Panel Interface Signal Descriptions ...................................... 42 Table 13. Digital Video Port B Signal Descriptions........................................................... 43 Table 14. Digital Video Port C Signal Descriptions........................................................... 44 Table 15. DVOB and DVOC Port Common Signal Descriptions ...................................... 45 Table 16. Intel(R) 852GME GMCH AGP/DVO Pin Muxing.................................................. 46 Table 17. Analog Display Signal Descriptions .................................................................. 47 Table 18. Graphics GPIO Signal Descriptions.................................................................. 48 Table 19. Voltage References, PLL Power....................................................................... 50 Table 20. Full and Warm Reset Waveforms..................................................................... 53 Table 21. Host Signal Reset and Power Managed States ............................................... 54 Table 22. System Memory Signal Reset and Power Managed States............................. 55 Table 23. Hub Interface Signal Reset and Power Managed States ................................. 56 Table 24. GMCH DVO Signal Reset and Power Managed States ................................... 57 Table 25. GMCH GPIO Signal Reset and Power Managed States.................................. 60 Table 26. GMCH LVDS Signal Reset and Power Managed States ................................. 61 Table 27. Device Number Assignment ............................................................................. 64 Table 28. Assignment Nomenclature for Access Attributes ............................................. 64 Table 29. GMCH/MCH Configuration Space - Device #0, Function#0............................. 71 Table 30. Attribute Bit Assignment.................................................................................... 86 Table 31. PAM Registers and Associated System Memory Segments............................ 88 Table 32. Host-Hub interface Bridge/System Memory Controller Configuration Space (Device #0, Function#1)........................................................................................... 104 Table 33. Configuration Process Configuration Space (Device#0, Function #3) ........... 126 Table 34. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Configurations ..................... 133 Table 35. Device 1 is the Virtual PCI to AGP Bridge (Device #1, Function #0)) ............ 134 Table 36. Integrated Graphics Device Configuration Space (Device #2, Function#0)... 149 Table 37. System Memory Segments and Their Attributes ............................................ 164 Table 38. Pre-allocated System Memory........................................................................ 166 Table 39. SMM Space Transaction Handling ................................................................. 171 Table 40. Relation of DBI Bits to Data Bits ..................................................................... 177 Table 41. Data Bytes on SO-DIMM Used for Programming DDR SDRAM Registers ... 179 Table 42. Dual Display Usage Model ............................................................................. 190 Table 43. Display Configuration Space .......................................................................... 198 Table 44. Display Configuration Space .......................................................................... 199 Table 45. Fast Write Initialization.................................................................................... 202 Table 46. PCI Commands Supported by the GMCH/MCH When Acting as a FRAME# Target....................................................................................................................... 202 Table 47. Enhanced Intel SpeedStep(R) Technology Overview........................................ 206 Table 48. Absolute Maximum Ratings ............................................................................ 209
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Table 49. Intel(R) 852GM/852GME/852GMV GMCH and Intel(R) 852PM MCH Package Thermal Resistance................................................................................................. 210 Table 50. Power Characteristics ..................................................................................... 211 Table 51. Signal Groups ................................................................................................. 213 Table 52. DC Characteristics .......................................................................................... 216 Table 53. DAC DC Characteristics: Functional Operating Range (VCCDAC = 1.5 V 5%)224 Table 54. DAC Reference and Output Specifications .................................................... 224 Table 55. Differential Signals in the XOR Chains ........................................................... 225 Table 56. XOR Chains Exclusion List ............................................................................. 226 Table 57. XOR Mapping ................................................................................................. 227 Table 58. Voltage Levels and Ball Out for Voltage Groups ............................................ 238 Table 59. State of Power Planes in C/S States .............................................................. 240 Table 60. Strapping Signals and Configuration .............................................................. 241 Table 61. Intel(R) 852GME GMCH Ballout Table .............................................................. 244 Table 62. Intel(R) 852PM MCH Ballout Table.................................................................... 261
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Revision History
Revision Number -001 -002 Initial release Updates include: * Added support for Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology * Updated Reference Documents table -003 Updates include: * Added support for Intel Celeron D processor on 90 nm process and in the 478-pin package -004 Updates include: * Added Electrical Characteristics as Chapter 6 * Testability is now Chapter 7 * Intel 852GME GMCH and 852PM MCH Strap Pins is now Chapter 8
(R) (R) (R) (R) (R)
Description
Revision Date June 2003 May 2004
June 2004
April 2005
* Ballout and Package Information is now Chapter 9
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Intel(R) 852PM Chipset MCH Features
Processor/Host Bus Support Mobile Intel(R) Pentium(R) 4 processor supporting Hyper-Threading Technology on 90-nm process technology Mobile Intel(R) Pentium(R) 4 processor Intel(R) Celeron(R) processor Intel(R) Celeron(R) D processor on 90 nm process and in the 478-pin package Source synchronous double pumped Address (2X) Source synchronous quad pumped Data (4X) Supports a subset of the Enhanced Mode Scalable Bus Protocol Intel Pentium 4 processor system bus interrupt delivery Supports processor system bus at 400 & 533 MHz Supports host Dynamic Bus Inversion (DBI) Supports 32-bit host bus addressing 8-deep, In-Order-Queue AGTL+ bus driver technology with integrated AGTL termination resistors Supports Enhanced Intel SpeedStep(R) technology Memory System Directly supports one DDR SDRAM channel, 64-bits wide Supports 200/266/333 MHz DDR SDRAM devices with max of 2 Double-Sided SODIMMs with unbuffered PC1600/PC2100 DDR SDRAM. Supports 128-Mbit, 256-Mbit, and 512-Mbit technologies System memory support up to 1-GB with x16 devices and up to 2-GB with high density 512-Mbit devices All supported devices have 4 banks Supports up to 16 simultaneous open pages ECC only supported with internal graphics System Interrupts Supports Intel 8259 and processor system bus interrupt delivery mechanism Supports interrupts signaled as upstream Memory Writes from PCI and hub interface MSI sent to the CPU through the processor system bus IOxAPIC in ICH4-M provides redirection for upstream interrupts to the system bus Accelerated Graphics Port (AGP) interface Supports a single AGP device Supports AGP 2.0 including 1X, 2X, and 4X AGP data transfers and 2X/4X Fast Write protocol Supports only 1.5 V AGP electricals 32 deep AGP request queue PCI semantic (FRAME# initiated) accesses to DDR SDRAM are snooped AGP semantic (PIPE# and SBA) accesses to DDR SDRAM are not snooped Hierarchical PCI configuration mechanism Delayed transaction support 32-bit upstream address support for inbound AGP and PCI cycles 32-bit downstream address support for outbound PCI and Fast Write cycles AGP Busy/Stop Protocol Hub interface to ICH4-M 266 MB/s point-to-point hub interface to ICH4-M 66 MHz base clock Power Management SMRAM space remapping to A0000h (128 kB) Supports extended SMRAM space above 256-MB, additional 1-MB TSEG from Top of Memory, cacheable (cacheability controlled by CPU) APM Rev 1.2 compliant power management Supports Suspend to System Memory (S3), Suspend to Disk (S4) and Hard Off/Total Reboot (S5) ACPI 1.0b, 2.0 Support Package 732-pin Micro-FCBGA (37.5 x 37.5 mm)
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Figure 1. Intel(R) 852PM GMCH Chipset System Block Diagram
Intel Processor
400/533MHz PC2100/PC2700 AGP 2.0 AGP Controller
852PM MCH 732 Micro-FCBGA
266/333MHz DDR
ATA100 IDE (2)
266 MHz HUB Interface
LAN
Intel 82801DBM
USB 2.0/1.1 (6)
ICH4-M 421 BGA
PCI 33MHz Audio Codec AC'97 2.2 Cardbus LPC I/P Audio Codec FWH SIO Moon2
KBC
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Intel(R) 852GME Chipset GMCH Features
Note: The Intel(R) 852GME chipset GMCH shares the same chipset features as the Intel 852PM chipset MCH along with the following additional integrated graphics features. Memory System ECC not supported with AGP Integrated Graphics Features Up to 64 MB of dynamic video memory allocation Display Image Rotation Core Frequency * Max 266 MHz graphics core frequency support at 1.5V * Display Core frequency of 133, 200, 250 266 MHz * Render Core frequency of 100,133, 200, 250, 266 MHz Video Stream Decoder HW Motion Compensation for MPEG2 All format decoder (18 ATSC formats) supported Dynamic Bob and Weave support for Video Streams Support for standard definition DVD quality encoding at low CPU utilization Video Overlay Single high quality scalable Overlay and second Sprite to support second Overlay Multiple Overlay functionality provided via Arithmetic Stretch BLT (Block Transfer) 5-tap horizontal, 3-tap vertical filtered scaling Multiple Overlay formats Direct YUV from Overlay to TV-out Independent Gamma Correction Independent Brightness / Contrast / Saturation Independent Tint / Hue support Destination Colorkeying Source Chromakeying Display Analog Display Support * 350 MHz integrated 24-bit RAMDAC Dual independent pipe support * Concurrent: Different images and native display timings on each display device DVO support * Two Digital Video Out (DVO) port 2D Graphics Features Optimized 128-bit BLT engine Ten programmable and predefined monochrome patterns Alpha Stretch Blt (via 3D pipeline) Anti-aliased lines Hardware-based BLT Clipping and Scissoring 32-bit Alpha Blended cursor 64 x 64 3-color Transparent cursor Color Space Conversion 3 Operand Raster BLTs ROP support 3D Graphics Features 3D Setup and Render engine Viewpoint Transform and Perspective Divide Triangle Lists, Strips and Fans support Indexed Vertex and Flexible Vertex formats Pixel accurate Fast Scissoring and Clipping operation Backface Culling support DirectX* and OGL support Anti-Aliased and Sprite Points support High quality performance Texture Engine 266-MegaTexel/s peak performance Per Pixel Perspective Corrected Texture Mapping Single Pass Texture Compositing (MultiTextures) at rate Enhanced Texture Blending functions Twelve Level of Detail MIP map sizes from 1x1 to 2Kx2K Alpha and Luminance Maps Texture Chromakeying Bilinear, Trilinear, and Anisotropic MIPMapped Filtering Cubic Environment Reflection Mapping Embossed Bump-Mapping DXTn Texture Decompression FX1 Texture Compression Flat and Gouraud Shading Color Alpha Blending for Transparency Vertex and Programmable Pixel Fog
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supported * Max 165 MHz dot clock * Variety of DVO devices supported * Compliant with DVI Specification 1.0 Dedicated LFP LVDS interface * Single or dual channel LVDS panel support up UXGA panel resolution with frequency range from 25 MHz to 112 MHz (single channel/dual channel) * Supports data format of 18-bpp * Compliant with ANSI/TIA/EIA -6441995 specification * SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock * LCD panel power sequencing compliant with SPWG timing specification * Integrated PWM interface for LCD backlight inverter control * Bi-linear Panel fitting
Color Specular Lighting Z Bias support 16 and 24-bit Z Buffering 16 and 24-bit W Buffering 8-bit Stencil Buffering Double and Triple Render Buffer support Maximum 3D resolution of 1600x1200 at 85-Hz (contact your Intel Field Representative for detailed display information, i.e. pixel depths, etc.) Fast Clear support
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Figure 2. Intel(R) 852GME GMCH Chipset System Block Diagram
Intel Processor CRT RGB 400/533 MHz FSB LVDS Panel
DVO Device/ AGP Graphic Controller
852GME GMCH 732 Micro-FCBGA DVO/AGP
PC2100/PC2700
266/333 MHz DDR
ATA100 IDE (2)
266 MHz Hub Interface
LAN
Intel 82801DB ICH4-M 421 BGA USB 2.0/1.1 (6) PCI 33MHz
Moon2
Audio Codec
AC'97 2.2 LPC I/P
Cardbus
Audio Codec
FWH
SIO KBC
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1
Overview
This datasheet provides Intel's specifications for the Intel(R) 852PM and Intel(R) 852GME chipset based systems. The Intel(R) 852PM chipset MCH is designed for use with the Mobile Intel(R) Pentium(R) 4 processor, Mobile Intel(R) Pentium(R) 4 Processor supporting Hyper-Threading Technology on 90-nm process technology, Intel(R) Celeron(R) processor or the Intel(R) Celeron(R) D processor on 90 nm process and in the 478-pin package. The Intel MCH manages the flow of information between its five interfaces: the system bus interface, the system memory interface, the AGP interface, and the hub interface. The Intel(R) 852GME chipset GMCH is designed for use with the Mobile Intel Pentium 4 processor, Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology, Intel Celeron processor or the Intel(R) Celeron(R) D processor on 90 nm process and in the 478-pin package. The GMCH manages the flow of information between its seven interfaces: the system bus interface, the system memory interface, the analog VGA port, the DVOB and C interfaces, the hub interface, and the LVDS panel interface. All recommendations will apply to all platforms unless specified. Any references to GMCH apply to both platforms unless otherwise specified. Any references to Mobile Intel Pentium 4 processor also applies to Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90nm process technology unless specified. Any references to the Intel Celeron processor also apply to the Intel Celeron D processor on 90 nm process and in the 478-pin package unless specified.
1.1
Terminology
Term
AGTL+ DDC DPMS I2C CRT LCD BLI Core CPU DBI
Description
Advanced Gunning Transceiver Logic + (AGTL+) bus Display Data Channel (standard created by VESA) Display Power Management Signaling (standard created by VESA) Inter-IC (a two wire serial bus created by Philips) Cathode Ray Tube Liquid Crystal Display Backlight Inverter The internal base logic in the Intel 852GME/852PM GMCH Central Processing Unit Dynamic Bus inversion
(R)
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Term
DBL DVO DVI* Display Brightness Link Digital Video Out
Description
Digital Visual Interface is the interface specified by the DDWG (Digital Display Working Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed TMDS protocol Dynamic Video Memory Technology Extended Display Identification Data A Full GMCH Reset is defined in this document when RSTIN# is asserted Graphics and Memory Controller Hub The proprietary interconnect between the GMCH and the ICH4-M component. In this document, the hub interface cycles originating from or destined for the ICH4-M are generally referred to as "hub interface cycles." Hub cycles originating from or destined for the primary PCI interface on are sometimes referred to as "hub interface/PCI cycles" This term is used synonymously with processor Integrated Graphics Device
DVMT EDID Full Reset GMCH Hub Interface (HI)
Host IGD Intel 852GME GMCH
(R)
Refers to the GMCH component. Throughout this datasheet, the Intel /852GME GMCH will be referred to as the GMCH. Refers to the MCH component. Throughout this datasheet, the Intel 852PM MCH will be referred to as the MCH. Refers to both 852GME and 852PM chipset.
Intel 852PM MCH
(R)
Intel 852 chipset Family Intel 82801DBM ICH4M
(R)
(R)
The component contains the primary PCI interface, LPC interface, USB 2.0, ATA100, AC'97, and other I/O functions. It communicates with the GMCH over a proprietary interconnect called the hub interface. Throughout this datasheet, the (R) Intel 82801DBM ICH4-M component will be referred to as the ICH4-M Inter Processor Interrupt Local Flat Panel Low Voltage Differential Signals used for interfacing to LCD Flat Panels Message Signaled Interrupts. MSI allow a device to request interrupt service via a standard memory write transaction instead of through a hardware signal Front Side Bus. Connection between GMCH and the CPU. Also known as the Host interface Pulse Width Modulation Spread Spectrum Clocking
IPI LFP LVDS MSI
FSB
PWM SSC
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Term
System Bus
Description
Processor-to-GMCH interface. The Enhanced mode of the Scalable bus is the P6 Bus plus enhancements, consisting of source synchronous transfers for address and data, and system bus interrupt delivery. The Mobile Intel Pentium 4 processor and Intel Celeron processor implement a subset of Enhanced mode. Unified Memory Architecture with graphics memory for the IGD inside System Memory Video Data Link Physical PCI bus that is driven directly by the component. It supports 3.3 V, 33 MHz PCI or PCI0 2.2 compliant components. Communication between PCI0 and the GMCH occurs over the hub interface. Note that although the Primary PCI bus is referred to as PCI0, it is not PCI Bus #0 from a configuration standpoint. Accelerated Graphics Port. Refers to the AGP/PCI interface that is in the GMCH. It supports a 1.5 V, 66/266 MHz component. PIPE# and SBA cycles are generally referred to as AGP transactions. FRAME# cycles are generally referred to as AGP/PCI transactions. The physical bus that is driven directly by the AGP/PCI1 Bridge (Device #1) in the GMCH. This is the primary AGP bus. Graphics Aperture Re-map Table. This table contains the page re-map information used during AGP aperture address translations. Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.
UMA
VDL Primary PCI
AGP
AGP/PCI1
GART
GTLB
1.2
Reference Documents
Document
(R) (R)
Document No./Location
http://www.intel.com/design/mobile/datashts/250686. htm http://www.intel.com/design/mobile/datashts/251308. htm http://www.intel.com/design/mobile/datashts/300302. htm http://www.intel.com/design/celeron/datashts/302353. htm www.pcisig.com http://developer.intel.com/design/mobile/datashts/252 337.htm
Mobile Intel Pentium 4 Processor-M Datasheet (250686) Mobile Intel Celeron Processor on .13 Micron Process and in Micro-FCPGA Package (251308) Intel
(R) (R) (R)
Celeron M Processor Datasheet(300302)
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Intel Celeron D Processors 345, 340, 335, 330, 325, and 320 Datasheet PCI Local Bus Specification 2.2 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337)
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(R)
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Document
Document No./Location
http://www.teleport.com/~acpi/
Advanced Configuration and Power Management(ACPI) Specification 1.0b & 2.0 Advanced Power Management (APM) Specification 1.2 IA-32 Intel Architecture Software Developer Manual Volume 3: System Programming Guide
(R)
http://www.microsoft.com/hwdev/busbios/amp_12.ht m http://developer.intel.com/design/Pentium4/manuals/ 24547203.pdf
1.3
1.3.1
System Architecture Overview
Intel(R) 852GME GMCH System Architecture
The Intel 852GME GMCH component provides the processor interface, DDR SDRAM interface, display interface, and hub interface in an Intel 852GME chipset platform. The GMCH is optimized for use with the Mobile Intel Pentium 4 processor and the Intel Celeron processor. It supports a single channel of DDR SDRAM memory. The GMCH contains advanced power management logic. The Intel 852GME chipset platform supports the fourth generation mobile I/O Controller Hub (ICH4-M) to provide the features required by a mobile platform. The Intel 852GME GMCH are in a 732-pin Micro-FCBGA package and contain the following functionality: * Supports a single mobile Intel Pentium 4 processor configurations at 533 MHz * System SDRAM supports 266/333MHz (SSTL_2) DDR SDRAM * Up to 2 GB (with 256-Mbit technology and two SO-DIMMs) of PC2100/2700 DDR SDRAM with ECC * Digital display support through two DVO ports (165 MHz, 12-bit DVO) * Integrated 350 MHz, 24-bit RAMDAC with maximum pixel resolution support up to 1600x1200 at 85 Hz and up to 2048x1536 at 75 Hz * One Dedicated Dual Channel LFP LVDS interface with frequency range of 25 MHz to 112 MHz (single channel/dual channel) for support up to UXGA (1600 x 1200 @ 60 Hz) panel resolutions with maximum pixel depth of 18-bpp * AGP interface with 1X/2X/4X SBA/Data Transfer and 2X/4X Fast Write capability
1.3.2
Intel(R) 852PM MCH System Architecture
The Intel 852PM MCH component share the same features as the Intel 852GME GMCH component, except it does not support internal graphics nor any corresponding display features (i.e., LFP LVDS interface, DAC interface, and DVO interface). It only supports external AGP graphics.
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1.4
Processor Host Interface
Intel 852GME GMCH and 852PM MCH are optimized for the Mobile Intel Pentium 4 processor. The key features are: * Source synchronous double pumped address (2X) * Source synchronous quad pumped data (4X) * System Bus interrupt and side-band signal delivery * A System Bus frequency of 400/533 MHz (Dual processor is not supported) * AGTL+ termination resistors on all of the AGTL+ signals * 32-bit host bus addressing allowing the CPU to access the entire 4 GB of the memory address space The GMCH/MCH has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the host bus. The GMCH/MCH supports one outstanding defer cycle at a time; however, it supports only one to any particular I/O interface. Host initiated I/O cycles are positively decoded to the GMCH/MCH configuration space and subtractively decoded to the hub interface. Host initiated memory cycles are positively decoded to DDR SDRAM. Memory accesses initiated from the hub interface to DDR SDRAM will be snooped on the System Bus. Host initiated I/O cycles are decoded to AGP/PCI1, hub interface, or GMCH/MCH configuration space. Host initiated memory cycles are decoded to AGP/PCI1, hub interface, system memory. All memory accesses from the FSB that hit the graphics aperture are translated using an AGP address translation table. The GMCH/MCH access to graphics memory and AGP/PCI1 device accesses to non-cacheable system memory are not snooped on the FSB. Memory accesses initiated from AGP/PCI1 using PCI semantics and from hub interface to system memory will be snooped on the host bus.
1.4.1
Host Bus Error Checking
The Intel 852GME GMCH and Intel 852PM MCH do not generate nor check parity for Data, Address/Request, and Response signals on the processor bus.
1.5
Intel(R) 852PM and 852GME DDR SDRAM Interface
The System Memory controller directly supports the following: * One channel of PC1600/2100 SO-DIMM DDR SDRAM memory * DDR SDRAM devices with densities of 128-Mbit, 256-Mbit, and 512-Mbit technology * Maximum system memory support of two, double-sided SO-DIMMs (four rows populated) with up to 2 GB memory * Variable page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every row and a maximum of 16 pages may be opened simultaneously 2 GB of memory support is realized by utilizing a high density memory configuration.
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Table 1. SDRAM Memory Capacity
Technology Width System Memory Capacity 256 MB 512 MB 1 GB 256 MB 512 MB 1 GB System Memory Capacity with High Density 512 MB 1 GB 2 GB
128 Mb 256 Mb 512 Mb 128 Mb 256 Mb 512 Mb
16 16 16 8 8 8
The Intel 852PM MCH and Intel 852GME system memory interface supports a thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be triggered either by on-die thermal sensor, or by preset write bandwidth limits. Read throttle can also be triggered by an external input pin. The memory controller logic supports aggressive dynamic row power down features (SCKE) to help reduce power and supports Address and Control lines tri-stating when DDR SDRAM is in active power down or self refresh. The system memory architecture is optimized to maintain open pages (up to 16-kB page size) across multiple rows. As a result, up to 16 pages across four rows. To complement this, the GMCH will tend to keep pages open within rows, or will only close a single bank on a page miss. Intel 852PM MCH and Intel 852GME support only two bank memory technologies. The Intel 852GME GMCH and Intel 852PM MCH allow the memory interface to provide optional ECC error checking for DDR SDRAM data integrity. During DDR SDRAM writes, ECC is generated on a QWORD (64-bit) basis. Because the GMCH/MCH stores only entire cache lines in its internal buffers, partial QWORD writes initially cause a read of the underlying data, and the write-back into memory is no different from that of a complete cache line. During DDR SDRAM reads and the read of the data that underlies partial writes, the GMCH/MCH supports detection of single-bit and multiple-bit errors, and will correct single bit errors when correction is enabled.
1.6
GMCH Internal Graphics Interface
The GMCH provides a highly integrated graphics accelerator delivering high performance 3D, 2D, and video capabilities. With its interfaces to UMA using a DVMT configuration, analog display, LVDS, and digital display (e.g. flat panel), the GMCH provides a complete graphics solution. The GMCH also provides 2D hardware acceleration for block transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces processor load, and thus improves performance. High bandwidth access to data is provided through the system memory ports. The GMCH uses Tiling architecture to increase system memory efficiency and thus maximize effective rendering bandwidth.
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The GMCH has four display ports, one analog and three digital. These provide support for a progressive scan analog monitor, a dedicated dual channel LVDS panel and two DVO devices. The data that is sent out to the display port is selected from one of the two possible sources, pipe A or pipe B.
1.6.1
GMCH Analog Display Port
Intel 852GME GMCH has an integrated 350 MHz, 24-bit RAMDAC that can directly drive a progressive scan analog monitor pixel resolution up to 1600x1200 at 85-Hz refresh and up to 2048x1536 at 75-Hz refresh. The DAC port can be driven on Pipe A or Pipe B.
1.6.2
GMCH Integrated LVDS Port
The Intel 852GME GMCH has an integrated dual channel LFP Transmitter interface to support LVDS LCD panel resolutions up to UXGA with center and down spread SSC support of 0.5%, 1%, and 2.5% utilizing an external SSC clock. The display pipe provides panel up-scaling to fit a source image into a specific panel size as well as panning and centering support. The LVDS port is only supported on Pipe B. The LVDS port can only be driven on Pipe B, either independently or simultaneously with the DAC port.
1.6.3
GMCH Integrated DVO Port
The DVO B/C interfaces are compliant with the DVI Specification 1.0. When combined with a DVI compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the GMCH provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor, etc.). Intel 852GME GMCH provides a DVO B and DVO C port that are each capable of driving a 165 MHz pixel clock. When DVO B and DVO C are combined, the effective dot clock can be increased to 330 MHz to support a dual channel (12-bit per channel) TV-Out Encoder. The DVO B/C ports can be driven on Pipe A or Pipe B. If driven on port B, then the LVDS port must be disabled.
1.7
1.7.1
External AGP Graphics Interface
Intel(R) 852PM MCH and Intel(R) 852GME GMCH AGP Interface
A single AGP component is supported by the AGP interface. The AGP buffers operate only in 1.5 V mode. They are not 3.3 V safe. The AGP interface supports 1X/2X/4X AGP signaling and 2X/4X Fast Writes. AGP semantic cycles to DDR SDRAM are not snooped on the host bus. PCI semantic cycles to DDR SDRAM are snooped on the host bus. The GMCH/MCH support PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and downstream addressing is limited to 32bits for AGP and AGP/PCI transactions. The GMCH/MCH contains a 32-deep AGP request queue. High priority accesses are supported. All accesses from the AGP/PCI interface that fall
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within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked from a dedicated 66 MHz clock (GLCKIN). The AGP-to-host/core interface is asynchronous. The AGP interface should be powered-off or tri-stated without voltage on the interface during ACPI S3 or APM Suspend to RAM state. Refer to the AGP Busy and Stop Signals Specification for more information.
1.8
Hub Interface
A proprietary interconnect connects the GMCH/MCH to the ICH4-M chipset. All communication between the GMCH/MCH and the ICH4-M occur over the hub interface. The hub interface runs at 66 MHz or 266 MB/s.
1.9
Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH/MCH configuration space and subtractively decoded to hub interface. Host initiated system memory cycles are positively decoded to DDR SDRAM and are again subtractively decoded to hub interface if under 4 GB. System memory accesses from hub interface to DDR SDRAM will be snooped on the FSB.
1.10
Platform Clocking
The GMCH/MCH has the following clock input/output pins: * 400 MHz, Spread Spectrum, Low Voltage Differential BCLK, BCLK# for processor system bus * 533 MHz Spread Spectrum, Low Voltage Differential BCLK, BCLK# for processor system bus (Intel 852GME GMCH and Intel 852PM MCH only) * 66 MHz Spread Spectrum, 3.3 V GCLKIN for AGP and hub interface buffers * Four pairs of differential output clocks (SCK[4,3,1:0], SCK[4,3,1:0]#), 200/266 MHz, 2.5 V for system memory interface * 48 MHz, non-Spread Spectrum, 3.3 V DREFCLK for the Display Frequency Synthesis * 48 MHz or 66 MHz, Spread Spectrum, 3.3 V DREFSSCLK for the Display Frequency Synthesis * Up to 85 MHz, 1.5 V DVOBCCLKINT for TV-Out mode * DPMS clock for S1-M Clock Synthesizer chip(s) are responsible for generating the system host clocks, display and hub interface clocks, PCI clocks, and system memory clocks. The host target speed is 400 MHz or 533 MHz. The GMCH does not require any relationship between the BCLK host clock and the 66 MHz clock generated for the AGP and hub interface; they are asynchronous to each other. The
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AGP and hub interface run at a constant 66 MHz base frequency. The hub interface runs at 4X, while AGP transfers may be at 1X, 2X, or 4X. The following table indicates the frequency ratios between the various interfaces that the GMCH/MCH supports: Table 2. Intel(R) 852GME GMCH Interface Clocks
Interface Clock Speed CPU System Bus Frequency Ratio Reference 1:1 Synchronous 1:1 Synchronous Asynchronous Sample s Per Clock 4 2 2 AGP Spec Data Rate (Megasamples/s) 533 266 333 AGP Spec 8 8 8 AGP Spec Data Width (Bytes) Peak Bandwidth (MB/s) 4264 2128 2664 AGP Spec
CPU Bus DDR SDRAM
133 MHz 133 MHz 166 MHz
AGP
66 MHz
1.11
System Interrupts
The GMCH/MCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and the respective processor Interrupt delivery mechanism. The serial APIC Interrupt mechanism is not supported. The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub interface. PCI MSI interrupts are generated as Memory Writes. The GMCH/MCH decodes upstream Memory Writes to the range 0FEE0_0000h - 0FEEF_FFFFh from the AGP and hub interface as message-based interrupts. The GMCH/MCH forwards the Memory Writes along with the associated write data to the system bus as an Interrupt Message transaction. Since this address does not decode as part of main system memory, the write cycle and the write data does not get forwarded to system memory via the write buffer. The GMCH/MCH provides the response and HTRDY# for all Interrupt Message cycles including the ones originating from the GMCH/MCH. The GMCH/MCH also supports interrupt re-direction for upstream interrupt memory writes. For message based interrupts, system write buffer coherency is maintained by relying on strict ordering of Memory Writes. The GMCH/MCH ensure that all Memory Writes received from a given interface prior to an interrupt message Memory Write are delivered to the system bus for snooping in the same order that they occur on the given interface.
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Signal Description
This section describes the GMCH/MCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: I O I/O Input pin Output pin Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The GMCH integrates AGTL+ termination resistors, and AGTL+ signals are "inverted bus" style where a low voltage represents a logical 1. DVO buffers (1.5 V tolerant) AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling Environment DC and AC Specifications. The buffers are 1.5 V tolerant Compatible to hub interface 1.5 Stub series termination logic compatible signals (2.5 V tolerant) Low voltage TTL compatible signals (3.3 V tolerant) CMOS buffers (3.3 V tolerant) Low voltage differential signal interface Analog signal interface Voltage reference signal
DVO AGP
Hub SSTL_2 LVTTL CMOS LVDS Analog Ref
System Address and Data Bus signals are logically inverted signals. In other words, the actual values are inverted of what appears on the system bus. This must be taken into account and the addresses and data bus signals must be inverted inside the GMCH/MCH. All processor control signals follow normal convention: A 0 indicates an active level (low voltage), and a 1 indicates an active level (high voltage).
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2.1
Host Interface Signals
Signal Name ADS# Type I/O AGTL+ I/O AGTL+ O AGTL+ Description Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH/MCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth. Bus Priority Request: The GMCH/MCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The GMCH/MCH pull the processor bus BREQ0# signal low during CPURST#. The signal is sampled by the processor on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs. BREQ0# should be tristated after the hold time requirement has been satisfied. During regular operation, the GMCH/MCH will use BREQ0# as an early indication for FSB Address and Ctl input buffer and sense amp activation. CPURST# O AGTL+ CPU Reset: The CPURST# pin is an output from the GMCH/MCH. The GMCH/MCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is asserted and for approximately 1 ms after RESET# is deasserted. The CPURST# allows the processor to begin execution in a known state. Note that the ICH4-M must provide CPU strap set-up and hold-times around CPURST#. This requires strict synchronization between GMCH/MCH, CPURST# deassertion and ICH4-M driving the straps. DBSY# DEFER# I/O AGTL+ O AGTL+ I/O AGTL+ Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: GMCH/MCH will generate a deferred response as defined by the rules of the GMCH/MCH's Dynamic Defer policy. The GMCH/MCH will also use the DEFER# signal to indicate a CPU retry response. Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the associated signals are inverted or not. DINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DINV# DINV[3]# DINV[2]# DINV[1]# DINV[0]# Data Bits HD[63:48]# HD[47:32]# HD[31:16]# HD[16:0]#
Table 3. Host Interface Signal Descriptions
BNR#
BPRI#
BREQ0#
I/O AGTL+
DINV[3:0]#
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Signal Name DPSLP#
Type I CMOS
Description Deep Sleep #: This signal comes from the ICH4-M device, providing an indication of C3 and C4 state control to the CPU. Deassertion of this signal is used as an early indication for C3 and C4 wake up (to active HPLL). Note that this is a low Voltage CMOS buffer operating on the FSB VTT power plane.
DRDY#
I/O AGTL+
Data Ready: Asserted for each cycle that data is transferred.
HA[31:3]#
I/O AGTL+
Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH/MCH drive HA[31:3]# during snoop cycles on behalf of hub interface. HA[31:3]# are transferred at 2X rate. Note that the address is inverted on the CPU bus. Host Address Strobe: HA[31:3]# connects to the CPU address bus. During CPU cycles, the source synchronous strobes are used to transfer HA[31:3]# and HREQ[4:0]# at the 2X transfer rate. Strobe HADSTB[0]# HADSTB[1]# Address Bits HA[16:3]#, HREQ[4:0]# HA[31:17]#
HADSTB[1:0]#
I/O AGTL+
HD[63:0]#
I/O AGTL+ I/O AGTL+
Host Data: These signals are connected to the CPU data bus. HD[63:0]# are transferred at 4X rate. Note that the data signals are inverted on the CPU bus. Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4X transfer rate. Strobe HDSTBP[3]#, HDSTBN[3]# HDSTBP[2]#, HDSTBN[2]# HDSTBP[1]#, HDSTBN[1]# HDSTBP[0]#, HDSTBN[0]# Data Bits HD[63:48]#, DINV[3]# HD[47:32]#, DINV[2]# HD[31:16]#, DINV[1]# HD[15:0]#, DINV[0]#
HDSTBP[3:0]# HDSTBN[3:0]#
HIT#
I/O AGTL+ I/O AGTL+ I/O AGTL+
Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface snoopable access to system memory is allowed when HLOCK# is asserted by the CPU.
HITM#
HLOCK#
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Signal Name HREQ[4:0]#
Type I/O AGTL+
Description Host Request Command: Defines the attributes of the request. HREQ[4:0]# are transferred at 2X rate. Asserted by the requesting agent during both halves of the Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the GMCH/MCH Host Bridge are defined in the Host Interface section of this document.
HTRDY# RS[2:0]#
O AGTL+ O AGTL+
Host Target Ready: Indicates that the target of the processor transaction is able to enter the data transfer phase. Response Status: Indicates the type of response according to the following the table: RS[2:0]# 000 001 010 011 100 101 110 111 Response type Idle state Retry response Deferred response Reserved (not driven by GMCH/MCH) Hard Failure (not driven by GMCH/MCH) No data response Implicit Write back Normal data response
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2.2
DDR SDRAM Interface
Signal Name SCS[3:0]# Type O SSTL_2 Description Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These signals can be toggled on every rising system memory clock edge (SCMDCLK). SMA[12:0] SBA[1:0] O SSTL_2 O SSTL_2 Multiplexed Memory Address: These signals are used to provide the multiplexed row and column address to the DDR SDRAM. Bank Select (Memory Bank Address): These signals define which banks are selected within each DDR SDRAM row. The SMA and SBA signals combine to address every possible location within a DDR SDRAM device. DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the system memory commands. DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with SCS#) to define the system memory commands. Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Data Lines: These signals are used to interface to the DDR SDRAM data bus. NOTE: Intel 852GME/852PM: ECC error detection is not supported by the SDQ[71:64] signals if AGP interface is enabled
Table 4. DDR SDRAM Interface Descriptions
SRAS#
O SSTL_2
SCAS#
O SSTL_2
SWE#
O SSTL_2
SDQ[71:0]
I/O SSTL_2
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Signal Name SDQS[8:0]
Type I/O SSTL_2
Description Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group. SDQS[7] -> SDQ[63:56] SDQS[6] -> SDQ[55:48] SDQS[5] -> SDQ[47:40] SDQS[4] -> SDQ[39:32] SDQS[3] -> SDQ[31:24] SDQS[2] -> SDQ[23:16] SDQS[1] -> SDQ[15:8] SDQS[0] -> SDQ[7:0] NOTE: Intel 852GME/852PM: ECC error detection is not supported by the SDQ[71:64] signals if AGP interface is enabled
SCKE[3:0]
O SSTL_2
Clock Enable: These pins are used to signal a self-refresh or power down command to the DDR SDRAM array when entering system suspend. SCKE is also used to dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR SDRAM row. These signals can be toggled on every rising SCK edge. Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not inverted. Data Mask: When activated during writes, the corresponding data groups in the DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be sampled on both edges of the data strobes. NOTE: Intel 852GME/852PM: ECC error detection is not supported by the SDQ[71:64] signals if AGP interface is enabled
SMAB[5,4,2,1]
O SSTL_2
SDM[8:0]
O SSTL_2
RCVENOUT#
O SSTL_2
Reserved: No connect.
RCVENIN#
O SSTL_2
Reserved: No connect.
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2.3
AGP Interface Signals
Unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts.
2.3.1
AGP Addressing Signals
Table 5. AGP Addressing Signal Descriptions
Signal Name GPIPE# Type I AGP Description Pipelined Read: This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus. During SBA Operation: This signal is not used if SBA (Side Band Addressing) is selected. During FRAME# Operation: This signal is not used during AGP FRAME# operation. PIPE# is a sustained tri-state signal from masters (graphics controller), and is an input to the GMCH/MCH. GSBA[7:0] I AGP Side-band Address: These signals are used by the AGP master (graphics controller) to pass address and command to the GMCH/MCH. The SBA bus and AD bus operate independently. That is, transactions can proceed on the SBA bus and the AD bus simultaneously. During PIPE# Operation: These signals are not used during PIPE# operation. During FRAME# Operation: These signals are not used during AGP FRAME# operation. NOTE: When sideband addressing is disabled, these signals are isolated (no external/internal pull-ups are required).
The AGP interface contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when the device is first being configured after reset.
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2.3.2
AGP Flow Control Signals
Table 6. AGP Flow Control Signals
Signal Name GRBF# Type I AGP Description Read Buffer Full: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH/MCH is not allowed to initiate the return low priority read data. That is, the GMCH/MCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation. GWBF# I AGP Write-Buffer Full: indicates if the master is ready to accept Fast Write data from the GMCH/MCH. When WBF# is asserted the GMCH/MCH is not allowed to drive Fast Write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation.
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2.3.3
AGP Status Signals
Table 7. AGP Status Signal Descriptions
Signal Name GST[2:0] Type O AGP Description Status: Provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be ignored. ST[2:0] 000 001 010 011 100 101 110 111 Meaning Previously requested low priority read data is being returned to the master Previously requested high priority read data is being returned to the master The master is to provide low priority write data for a previously queued write command The master is to provide high priority write data for a previously queued write command. Reserved Reserved Reserved The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#.
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2.3.4
AGP Strobes
Table 8. AGP Strobe Descriptions
Signal Name GADSTB[0] Type I/O AGP I/O AGP Description Address/Data Bus Strobe-0: provides timing for 2X and 4X data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1: Provides timing for 2X and 4X data on AD[31:16] and C/BE[3:2]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1 Complement: With AD STB1, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is providing the data will drive this signal. Sideband Strobe: Provides timing for 2X and 4X data on the SBA[7:0] bus. It is driven by the AGP master after the system has been configured for 2X or 4X sideband address mode. Sideband Strobe Complement: The differential complement to the SB_STB signal. It is used to provide timing 4X mode.
GADSTB#[0]
GADSTB[1]
I/O AGP I/O AGP
GADSTB#[1]
GSBSTB
I AGP I AGP
GSBSTB#
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2.3.5
AGP/PCI Signals-Semantics
For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similarly to their semantics in the PCI 2.1 specification, as defined below.
Table 9. AGP/PCI Signals-Semantics Descriptions
Signal Name GFRAME# Type I/O AGP G_FRAME: Frame. During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations. During Fast Write Operation: Used to frame transactions as an output during Fast Writes. During FRAME# Operation: G_FRAME# is an output when the GMCH/MCH acts as an initiator on the AGP Interface. G_FRAME# is asserted by the GMCH/MCH to indicate the beginning and duration of an access. G_FRAME# is an input when the GMCH/MCH acts as a FRAME#based AGP target. As a FRAME#-based AGP target, the GMCH/MCH latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which GMCH/MCH samples FRAME# active. GIRDY# I/O AGP G_IRDY#: Initiator Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# is an output when GMCH/MCH acts as a FRAME#-based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus initiator's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred. GTRDY# I/O AGP G_TRDY#: Target Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_TRDY# is an input when the GMCH/MCH acts as an AGP initiator and is an output when the GMCH/MCH acts as a FRAME#-based AGP target. The assertion of G_TRDY# indicates the target's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. Description
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Signal Name GSTOP#
Type I/O AGP G_STOP#: Stop.
Description
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_STOP# is an input when the GMCH/MCH acts as a FRAME#-based AGP initiator and is an output when the GMCH/MCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface.
GDEVSEL#
I/O AGP
G_ DEVSEL#: Device Select. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The GMCH/MCH asserts G_DEVSEL# based on the DDR SDRAM address range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP master has recognized a PCI cycle to it.
GREQ#
I AGP
G_REQ#: Request. During SBA Operation: This signal is not used during SBA operation. During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based operation.
GGNT#
O AGP
G_GNT#: Grant. During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings. G_AD[31:0]: Address/Data Bus. During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to transfer both address and data information on the AGP interface. During SBA Operation: The G_AD[31:0] signals are used to transfer data on the AGP interface.
GAD[31:0]
I/O AGP
GCBE#[3:0]
I/O AGP
Command/Byte Enable. During FRAME# Operation: During the address phase of a transaction, the G_CBE[3:0]# signals define the bus command. During the data phase, the G_CBE[3:0]# signals are used as byte enables. The byte enables determine which byte lanes carry meaningful data. The commands issued on the G_CBE# signals during FRAME#-based AGP transactions are the same G_CBE# command described in the PCI 2.2 specification. During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE# signals carry command information. Refer to the AGP 2.0 Interface Specification, Revision 2.0 for the definition of these commands. The command encoding used during PIPE#-based AGP is different than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus). During SBA Operation: These signals are not used during SBA operation.
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Signal Name GPAR
Type I/O AGP Parity.
Description
During FRAME# Operation: G_PAR is driven by the GMCH/MCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. G_PAR is driven by the GMCH/MCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface logic within the GMCH/MCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as an input to reset its internal logic.
2.4
Hub Interface Signals
Signal Name HL[10:0] HLSTB HLSTB# Type I/O I/O I/O Description Packet Data: Data signals used for HI read and write operations Packet Strobe: One of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: One of two differential strobe signals used to transmit or receive packet data over HI.
Table 10. Hub Interface Signals
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2.5
Clocks
Signal Name Type Description
Table 11. Clock Signals
Host Processor Clocking BCLK BCLK# I CMOS Differential Host Clock In: These pins receive a buffered host clock from the external clock synthesizer. This clock is used by all of the GMCH/MCH logic that is in the Host clock domain (host, hub and system memory). The clock is also the reference clock for the graphics core PLL. This is a low voltage differential input.
System Memory Clocking SCK[5:0] O SSTL_2 Differential DDR SDRAM Clock: SCK and SCK# pairs are differential clock outputs. The crossing of the positive edge of SCK and the negative edge of SCK# is used to sample the address and control signals on the DDR SDRAM. There are 3 pairs to each SO-DIMM. NOTE: Intel 852GME ECC error detection is supported by the SCK[2] and SCK[5] signals. SCK[5:0]# O SSTL_2 Complementary Differential DDR SDRAM Clock: These are the complimentary differential DDR SDRAM clock signals. NOTE: Intel 852GME/852PM: ECC error detection is supported by the SCK[2]# and SCK[5]# signals. DVO/Hub Input Clocking GCLKIN I CMOS DVO Clocking DVOBCLK DVOBCLK# O DVO Differential DVO Clock Output: These pins provide a differential pair reference clock that can run up to 165 MHz. DVOBCLK corresponds to the primary clock out. DVOBCLK# corresponds to the primary complementary clock out. DVOCCLK DVOCCLK# O DVO Differential DVO Clock Output: These pins provide a differential pair reference clock that can run up to 165 MHz. DVOCCLK corresponds to the primary clock out. DVOCCLK# corresponds to the primary complementary clock out. Input Clock: 66 MHz, 3.3 V input clock from external buffer DVO/hub interface.
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Signal Name DVOBCCLKINT
Type I DVO
Description DVOBC Pixel Clock Input/Interrupt: This input can be programmed to be either a TV reference clock input from a TV encoder or an Interrupt input pin for LFP display Hot Plug support. DVOBC Pixel Clock Input: This signal may be configured as the reference clock input from a TV-OUT device. The maximum input frequency for this signal is 85 MHz. DVOBC Interrupt: This signal may be configured as an interrupt input for Hot plug support. DVOBCCLKINT needs to be pulled down if the signal is NOT used.
DPMS
I DVO
Display Power Management Signaling: This signal is used only in mobile systems to act as the DREFCLK in certain power management states (i.e. Display Power Down Mode); DPMS Clock is used to refresh video during S1-M. Clock Chip is powered down in S1-M. DPMS should come from a clock source that runs during S1-M and needs to be 1.5 V. So, an example would be to use a 1.5 V version of SUSCLK from ICH4-M.
DAC Clocking DREFCLK I LVTTL Display Clock Input: This pin is used to provide a 48 MHz input clock to the Display PLL that is used for 2D/Video and DAC.
LVDS LCD Flat Panel Clocking DREFSSCLK I LVTTL Display SSC Clock Input: This pin provides a 48 MHz or 66 MHz input clock (SSC or non-SSC) to the Display PLL B.
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2.6
GMCH Internal Graphics Display Signals
The Intel 852GME internal graphics device has support for four display ports: a dedicated LVDS panel interface, two DVO ports, and an analog VGA port.
2.6.1
Dedicated LVDS Panel Interface
Table 12. Dedicated LVDS Panel Interface Signal Descriptions
Name ICLKAP Type O LVDS ICLKAM O LVDS IYAP[3:0] O LVDS IYAM[3:0] O LVDS ICLKBP O LVDS ICLKBM O LVDS IYBP[3:0] O LVDS IYBM[3:0] O LVDS 1.25 V 225 mV 1.25 V225 mV 1.25 V225 mV 1.25 V225 mV 1.25 V225 mV 1.25 V225 mV 1.25 V225 mV Voltage 1.25 V 225 mV Description Channel A differential clock pair output (true): 245-800 MHz Channel A differential clock pair output (compliment): 245-800 MHz. Channel A differential data pair 3:0 output (true): 245-800 MHz. Channel A differential data pair 3:0 output (compliment): 245-800 MHz. Channel B differential clock pair output (true): 245-800 MHz. Channel B differential clock pair output (compliment): 245-800 MHz. Channel B differential data pair 3:0 output (true): 245-800 MHz. Channel B differential data pair 3:0 output (compliment): 245-800 MHz.
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2.6.2
Digital Video Port B (DVOB)
Table 13. Digital Video Port B Signal Descriptions
Signal Name DVOBD[11:0] Type O DVO Description DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the lower 12-bits of pixel data. DVOBD[11:0] should be left as left as NC ("Not Connected") if not used. DVOBHSYNC O DVO DVOBVSYNC O DVO DVOBBLANK# O DVO Horizontal Sync: HSYNC signal for the DVOB interface. DVOBHSYNC should be left as left as NC ("Not Connected") if not used. Vertical Sync: VSYNC signal for the DVOB interface. DVOBVSYNC should be left as left as NC ("Not Connected") if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOBBLANK# is a programmable output pin driven by the GMCH/MCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOBBLANK# should be left as left as NC ("Not Connected") if not used. DVOBFLDSTL I DVO TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOB TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOBFLDSTL needs to be pulled down if not used.
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2.6.3
Digital Video Port C (DVOC)
Table 14. Digital Video Port C Signal Descriptions
Signal Name DVOCD[11:0] Type O DVO Description DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data. DVOCD[11:0] should be left as left as NC ("Not Connected") if not used. DVOCHSYNC O DVO DVOCVSYNC O DVO DVOCBLANK# O DVO Horizontal Sync: HSYNC signal for the DVOC interface. DVOCHSYNC should be left as left as NC ("Not Connected") if not used. Vertical Sync: VSYNC signal for the DVOC interface. DVOCVSYNC should be left as left as NC ("Not Connected") if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOCBLANK# is a programmable output pin driven by the GMCH/MCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOCBLANK# should be left as left as NC ("Not Connected") if not used. DVOCFLDSTL I DVO TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOC TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOCFLDSTL needs to be pulled down if not used.
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Table 15. DVOB and DVOC Port Common Signal Descriptions
Signal Name DVOBCINTR# Type I DVO ADDID[7:0] I DVO Description DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. ADDID[7:0]: These pins are used to communicate to the video BIOS when an external device is interfaced to the DVO port. NOTE: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC. Signal Name DVODETECT Type I DVO Description DVODETECT: This strapping signal indicates to the GMCH/MCH whether a DVO device is present or not. When a DVO device is connected, then DVODETECT = 0.
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2.6.4
GMCH DVO & I2C to AGP Pin Mapping
The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH/MCH has an internal pull-down on DVODETECT signal that will by default pull it low. For an AGP graphics device, pin should be pulled up high and the AGP/DVO Mux select bit in the SHIC (Device 0, function 0, offset 74h bit 1) register will be set to AGP mode (AGP/DVO Mux Strap = 1). Boards that use only Integrated Graphics should leave DVODETECT NC (No Connect). If board has digital display devices connected to the AGP/DVO interface, SBA [7:0] will act as straps for an ADDID.
Table 16. Intel(R) 852GME GMCH AGP/DVO Pin Muxing
DVO MODE DVOBD[0] DVOBD[1] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] DVOBD[8] DVOBD[9] DVOBD[10] DVOBD[11] DVOBCLK DVOBCLK# DVOBHSYNC DVOBVSYNC DVOBBLANK# DVOBFLDSTL AGP MODE GAD[3] GAD[2] GAD[5] GAD[4] GAD[7] GAD[6] GAD[8] GCBE#[0] GAD[10] GAD[9] GAD[12] GAD[11] GADSTB[0] GADSTB#[0] GAD[0] GAD[1] GCBE#[1] GAD[14] DVO MODE DVOCD[0] DVOCD[1] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6] DVOCD[7] DVOCD[8] DVOCD[9] DVOCD[10] DVOCD[11] DVOCCLK DVOCCLK# DVOCHSYNC DVOCVSYNC DVOCBLANK# DVOCFLDSTL AGP MODE GAD[19] GAD[20] GAD[21] GAD[22] GAD[23] GCBE#[3] GAD[25] GAD[24] GAD[27] GAD[26] GAD[29] GAD[28] GADSTB[1] GADSTB#[1] GAD[17] GAD[16] GAD[18] GAD[31] DVO MODE MI2CCLK MI2CDATA MDVICLK MDVIDATA MDDCCDATA MDDCCLK DVOBCINT# DVOBCCLKINT ADDID[7] ADDID[6] ADDID[5] ADDID[4] ADDID[3] ADDID[2] ADDID[1] ADDID[0] DVODETECT DPMS AGP MODE GIRDY# GDEVSEL# GTRDY# GFRAME# GAD[15] GSTOP# GAD[30] GAD[13] GSBA[7] GSBA[6] GSBA[5] GSBA[4] GSBA[3] GSBA[2] GSBA[1] GSBA[0] GPAR GPIPE#
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2.6.5
Analog Display
Table 17. Analog Display Signal Descriptions
Signal Name VSYNC Type O CMOS HSYNC O CMOS RED O Analog Description CRT Vertical Synchronization: This signal is used as the vertical sync signal. CRT Horizontal Synchronization: This signal is used as the horizontal sync signal. Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5- equivalent load on each pin (e.g., 75- resistor on the board, in parallel with the 75- CRT load). Red# (Analog Output): Tied to ground.
RED#
O Analog
GREEN
O Analog
Green (Analog Video Output): This signal is a CRT analog video output from the internal color palette DAC. The DAC is designed for a 37.5- equivalent load on each pin (e.g., 75- resistor on the board, in parallel with the 75- CRT load). Green# (Analog Output): Tied to ground.
GREEN#
O Analog
BLUE
O Analog
Blue (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5- equivalent load on each pin (e.g., 75-ohm resistor on the board, in parallel with the 75- CRT load). Blue# (Analog Output): Tied to ground.
BLUE#
O Analog
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2.6.6
Graphics General Purpose Input/Output Signals
Table 18. Graphics GPIO Signal Descriptions
GPIO I/F Total AGPBUSY# Type O CMOS Comments AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went active. Not active when the IGD is in any ACPI state other than D0. External Thermal Sensor Input: This signal is an active low input to the GMCH/MCH and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle. The GMCH/MCH can be optionally programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the triggering of this signal. Panel Power Sequencing Control Signals PANELVDDEN O CMOS PANELBKLTEN O CMOS PANELBKLTCTL O CMOS LVDS LCD Flat Panel Power Control: This signal is used to enable the power to the panel interface. LVDS LCD Flat Panel Backlight Enable: This signal is used to enable the backlight inverter (BLI). LVDS LCD Flat Panel Backlight Brightness Control: This signal is used as the Pulse Width Modulated (PWM) control signal to inverter for control the of backlight brightness. GPIO pins for DDC/GMBUS support LCLKCTLA O CMOS LCLKCTLB O CMOS DDCACLK I/O CMOS DDCADATA I/O CMOS DDCPCLK I/O CMOS DDCPDATA I/O CMOS SSC Chip Clock Control: Can be used to control an external clock chip with SSC control. If external SSC chip not used, may optionally use for DDC/GMBUS support. SSC Chip Data Control: Can be used to control an external clock chip for SSC control. If external SSC chip not used, may optionally use for DDC/GMBUS support. CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and the GMCH. CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the GMCH. Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the GMCH. Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH. GPIO pins for DDC/GMBUS support MI2CCLK I/O DVO DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset.
EXTTS_0
I CMOS
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GPIO I/F Total MI2CDATA
Type I/O DVO
Comments DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC data for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Clock: The signal is used as the DDC data for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC clock for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset.
MDVICLK
I/O DVO
MDVIDATA
I/O DVO
MDDCDATA
I/O DVO
MDDCCLK
I/O DVO
2.7
Power Sequencing Signal Description
GPIO I/F Total RSTIN# Type I CMOS PWROK I CMOS Power OK: Indicates that power to GMCH/MCH is stable. Comments Reset: Primary Reset, Connected to PCIRST# of ICH4-M.
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2.8
Voltage References, PLL Power
GPIO I/F Total
Table 19. Voltage References, PLL Power
Type Host Processor HXRCOMP HYRCOMP HXSWING HYSWING HDVREF[2:0] Analog Analog Analog Analog Ref Analog Ref Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. Host Voltage Swing (RCOMP reference voltage): These signals provide a reference voltage used by the FSB RCOMP circuit. Host Voltage Swing (RCOMP reference voltage): These signals provide a reference voltage used by the FSB RCOMP circuit. Host Data (input buffer) VREF: Reference voltage input for the data signals of the Host AGTL+ interface. Input buffer differential amplifier to determine a high versus low input voltage. Host Address (input buffer) VREF: Reference voltage input for the address signals of the Host AGTL+ interface. This signal is connected to the input buffer differential amplifier to determine a high versus low input voltage. Host Common Clock (Command input buffer) VREF: Reference voltage input for the common clock signals of the Host AGTL+ Interface. This signal is connected to the input buffer differential amplifier to determine a high versus low input voltage. FSB Power Supply: VTTLF is the low frequency connection from the board. This signal is the primary connection of power for GMCH. FSB Power Supply: VTTHF is the high frequency supply. It is for direct connection from an internal package plane to a capacitor placed immediately adjacent to the GMCH. NOTE: Not to be connected to power rail. System Memory SMRCOMP SMVREF_0 Analog Ref Analog System Memory RCOMP: This signal is used to calibrate the memory I/O buffers. Memory Reference Voltage (Input buffer VREF):Reference voltage input for Memory Interface. Input buffer differential amplifier to determine a high versus low input voltage. SMVSWINGH SMVSWINGL VCCSM VCCQSM Ref Analog Ref Analog Power Power RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the I/O buffers. RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the I/O buffers. Power supply for Memory I/O. Power supply for system memory clock buffers. Comments
HAVREF
HCCVREF
Ref Analog
VTTLF VTTHF
Power Power
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VCCASM
Power
Power supply for system memory logic running at the core voltage (isolated supply, not connected to the core). Hub Interface
HLRCOMP PSWING HLVREF VCCHL
Analog Analog Ref Analog Power
Hub Interface RCOMP: This signal is connected to a reference resistor in order to calibrate the buffers. RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers. Input buffer VREF: Input buffer differential amplifier to determine a high versus low input voltage. Power supply for Hub interface buffers DVO (Intel 852GME GMCH Only)
(R)
DVORCOMP GVREF VCCDVO GPIO VCCGPIO
Analog Analog Ref Analog Power
Compensation for DVO: This signal is used to calibrate the DVO I/O buffers. Input buffer VREF: Input buffer differential amplifier to determine a high versus low input voltage. Power supply for DVO
Power
Power supply for GPIO buffers DAC (Intel 852GME GMCH Only)
(R)
REFSET
Ref Analog
Resistor Set: Set point resistor for the internal color palette DAC.
VCCADAC VSSADAC
Power Power
Power supply for the DAC Ground supply for the DAC LVDS (Intel 852GME GMCH Only)
(R)
LIBG VCCDLVDS VCCTXLVDS VCCALVDS VSSALVDS
Analog Power Power Power Power
LVDS reference current: signal connected to reference resistor. Digital power supply. Data/Clk Tx power supply. Analog power supply. Ground supply for LVDS. Clocks
VCCAHPLL VCCAGPLL VCCADPLLA VCCADPLLB
Power Power Power Power
Power supply for the Host PLL. Power supply for the Hub/DVO PLL. Power supply for the display PLL A. Power supply for the display PLL B. Core
VCC VSS
Power Power
Power supply for the core. Ground supply for the chip.
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2.9
Reset States and Pull-up/Pull-downs
This section describes the expected states of the Intel 852GME GMCH and 852PM MCH I/O buffers. These tables refer only to the contributions on the interface from the GMCH/MCH and do NOT reflect any external influence (such as external pullup/pulldown resistors or external drivers). Legend: Z: Hi: 1: Low: 0: Term H/L: Pwrdn: Drive H/L: Input: PU, PD: External PU, PD: Intern:IG: Internal GFX: External GFX: Self-refresh: X: Tristate Outputs Pulled High High Pulled Low Low Normal internal termination devices are turned on high/low Power down Strong Drive high/low Input Buffer Weak internal pull-up, Weak internal pull down Must be externally pulled-up or pulled down Internal GFX Must keep system memory running for display Can be in self-refresh CKE is not asserted, all other pins can be hi-z Do not Care
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2.9.1
Full and Warm Reset State
Figure 3 . Full and Warm Reset Waveforms
ICH4-M Power ICH4-M PWROK In 1 ms min ICH4-M PCIRST# Out GMCH/MCH RSTIN# In 1 ms 1 ms write to CF9h 1 ms min
GMCH/MCH CPURST# Out
GMCH/MCH Power
GMCH/MCH PWROK In
GMCH/MCH Reset State
Unknown
Full Reset
Warm Reset
Running
Warm Reset
Running
All register bits assume their default values during full reset. PCIRST# resets all internal flops and state machines (except for a few configuration register bits). A full reset occurs when PCIRST# (RSTIN#) and CPURST# are asserted and PWROK is deasserted. This means that all the registers are changed to their default values in the entire system. A warm reset (CPU only reset) occurs when PCIRST# (RSTIN#) is asserted and PWROK is asserted. CPU only reset drives only CPURST# and can be initiated by write of a bit in dedicated register and HALT special cycle. As a result, CPU only registers must be reset. Table 20 describes the reset states. The PWROK input pin is used to latch the GMCH/MCH strap values upon exiting S3. This imposes a system requirement in that the ICH4-M expects power to be removed (PWROK to go low) when SLP_S3# goes low. Table 20. Full and Warm Reset Waveforms
Reset State Full Reset Warm Reset Doesn't Occur Normal Operation L L H H RSTIN# L H L H PWROK
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Table 21. Host Signal Reset and Power Managed States
Host I/F Total ADS# BNR# BPRI# BREQ0# CPURST# DBSY# DEFER# DINV[3:0]# DPWR# DPSLP# DRDY# HA[31:3]# HADSTB[1:0]# HDB_63:0 HDSTBNB_3:0 HDSTBPB_3:0 HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# Before CPURST# Deassertion Term H Term H Term H Low Low Term H Term H Term H Low Input Term H TBD Term H Term H Term H Term H Term H Term H Input Term H Term H Term H Just out of CPURST# Term H Term H Term H Term H after 2 clocks Term H Term H Term H Term H Low Input Term H Term H after 3 clocks Term H Term H Term H Term H Term H Term H Input Term H Term H Term H C3 Term H Term H Term H Term H Term H Term H Term H Term H Term H Input Term H Term H Term H Term H Term H Term H Term H Term H Input Term H Term H Term H S1 Term H Term H Term H Term H Term H Term H Term H Term H Term H Input Term H Term H Term H Term H Term H Term H Term H Term H Input Term H Term H Term H S3 Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn S4/S5 Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
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Table 22. System Memory Signal Reset and Power Managed States
Host I/F Total SDQ[63:0] SDM[8:0] SDQS[7:0] Before CPURST# Deassertion Hi-Z Hi-Z Hi-Z Just out of CPURST# Hi-Z Hi-Z Hi-Z C3 Intern: IG Intern: IG Intern: IG If ECC not enabled, ECC clocks are Hi-Z. Intern: Hi-Z if self refresh, else toggling If ECC not enabled, ECC clocks are Hi-Z. Intern: Hi-Z if self refresh, else toggling Intern: IG Intern: IG Intern: IG Intern: IG Intern: IG Intern: IG Intern: IG Intern: IG Input Intern: IG S1 Hi-Z Hi-Z Hi-Z S3 Hi-Z Hi-Z Hi-Z S4/S5 Pwrdn Pwrdn Pwrdn
SCK[5:0]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pwrdn
SCK[5:0]# SMA[12:0] SMAB_5,4,2,1 SBA_1:0 SRAS# SCAS# SWE# SCS[3:0]# SCKE[3:0] RCVENIN# RCVENOUT#
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi Low Input X
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HiZ Hi Low Input Hi
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low Input Hi
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low Input Hi-Z
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
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Table 23. Hub Interface Signal Reset and Power Managed States
Host I/F Total HL[7:0] HL[10] HLSTB HLSTB# HL[9] HL[8] Before CPURST# Deassertion Term L Term L Term L TermL Input Low Just out of CPURST# Term L Term L Term L Term L Input Low C3 Term L Term L Term L Term L Input Low S1 Term L Term L Term L Term L Input Low S3 Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn S4/S5 Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
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Table 24. GMCH DVO Signal Reset and Power Managed States
Host I/F Total DVOCCLK# DVOBCLK# Hi-Z Hi-Z Before CPURST# Deassertion Just out of CPURST# C3 S1 S3 S4/S5
Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation
PD Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Input
Pwrdn
Pwrdn
DVOBHSYNC
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBVSYNC
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[1]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[0]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[3]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[2]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[5]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[4]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[6]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[9]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[8]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[11]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBD[10] DVOBCCLKINT
Hi-Z Input
Hi-Z Input
Pwrdn Pwrdn
Pwrdn Pwrdn
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Host I/F Total
Before CPURST# Deassertion
Just out of CPURST#
C3 Normal Operation Hi-Z External PU Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation
S1
S3
S4/S5
DVOBFLDSTL
Input
Input Hi-Z External PU
Input Hi-Z External PU Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled External PU
Pwrdn
Pwrdn
MDDCDATA
Hi-Z External PU
Pwrdn
Pwrdn
DVOCVSYNC
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCHSYNC
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCBLANK#
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[0]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[1]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[2]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[3]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[4]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[7]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[6]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[8]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[11]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[10] DVOBCINTR#
Hi-Z Input
Hi-Z Input
Pwrdn Pwrdn
Pwrdn Pwrdn
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Signal Description
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Host I/F Total
Before CPURST# Deassertion
Just out of CPURST#
C3 Normal Operation Normal Operation Normal Operation Normal Operation Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Input
S1
S3
S4/S5
DVOCFLDSTL
Input
Input
Input Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z if port not enabled Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Clocking
Pwrdn
Pwrdn
DVOBD[7]
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOBBLANK#
Hi-Z
Hi-Z
Pwrdn
Pwrdn
DVOCD[5]
Hi-Z
Hi-Z Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Input
Pwrdn
Pwrdn
MI2CDATA
Hi-Z External PU
Pwrdn
Pwrdn
MDVIDATA
Hi-Z External PU
Pwrdn
Pwrdn
MI2CCLK
Hi-Z External PU
Pwrdn
Pwrdn
MDDCCLK
Hi-Z External PU
Pwrdn
Pwrdn
MDVICLK DPMS
Hi-Z External PU Input
Pwrdn Pwrdn
Pwrdn Pwrdn
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Table 25. GMCH GPIO Signal Reset and Power Managed States
Host I/F Total RSTIN# PWROK Before CPURST# Deassertion Hi Hi Just out of CPURST# Hi Hi Hi Hi If analog display enabled, Normal Operation If analog display enabled, Normal Operation See C3 Operation External PU Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Hi Hi Hi Hi C3 Hi Hi S1 S3 Pwrdn Pwrdn S4/S5 Pwrdn Pwrdn
HSYNC
Low
Low
See ADPA Register
Pwrdn
Pwrdn
VSYNC AGPBUSY# EXTTS_0
Low External PU External PU
Low External PU External PU
See ADPA Register External PU External PU Normal Operatio n Normal Operatio n Low Low Hi-Z Hi Hi Hi Hi
Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn
LCLKCTLA
PU
PU
Pwrdn
Pwrdn
LCLKCTLB PANELVDDEN PANELBKLTEN PANELBKLTCTL DDCACLK DDCADATA DDCPCLK DDCPDATA
PU Hi-Z Hi-Z Hi-Z Hi Hi Hi Hi
PU Hi-Z Hi-Z Hi-Z Hi Hi Hi Hi
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
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Table 26. GMCH LVDS Signal Reset and Power Managed States
Host I/F Total Before CPURST# Deassertion Just out of CPURST# C3 S1 Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ Drive VSS/ HiZ S3 Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z Drive VSS/ Hi-Z S4/S5
IYAP[3:0]
Drive VSS
Drive VSS
Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation Normal Operation
Pwrdn
IYAM[3:0]
Drive VSS
Drive VSS
Pwrdn
ICLKAP
Drive VSS
DriveVSS
Pwrdn
ICLKAM
Drive VSS
Drive VSS
Pwrdn
IYBP[3:0]
Drive VSS
Drive VSS
Pwrdn
IYBM[3:0]
Drive VSS
Drive VSS
Pwrdn
ICLKBP
Drive VSS
Drive VSS
Pwrdn
ICLKBM
Drive VSS
Drive VSS
Pwrdn
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3
3.1
Register Description
Conceptual Overview of the Platform Configuration Structure
The Intel 852GME GMCH, Intel 852PM MCH and ICH4-M are physically connected by hub interface. From a configuration standpoint, the hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH/MCH and ICH4-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically attached to the ICH4-M and from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration standpoint. The AGP appears to system software to be real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus #0. The GMCH/MCH contains two PCI devices within a single physical component. The configuration registers for the three devices are mapped as devices residing on PCI bus #0. Device #0: Host-Hub Interface Bridge/DDR SDRAM Controller. Logically this appears as a PCI device residing on PCI bus #0. Physically, Device #0 contains the standard PCI registers, DDR SDRAM registers, the Graphics Aperture Controller registers, Hub Interface Control registers and other GMCH/MCH specific registers. Device #0 is divided into the following functions: Function #0: Host Bridge Legacy registers including Graphics Aperture Control registers, Hub Interface Configuration registers and Interrupt Control registers Function #1: DDR SDRAM Interface Registers Function #3: Intel Configuration Process Registers Device #1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing on PCI bus #0. Physically Device #1 contains the standard PCI-to-PCI bridge registers and the standard AGP/PCI configuration registers (including the AGP I/O and memory address mapping). Device #2: Integrated Graphics Controller. Logically this appears as a PCI device residing on PCI bus #0. Physically Device #2 contains the Configuration registers for 2D, 3D, and display functions. Table 27 shows the Device # assignment for the various internal GMCH/MCH devices.
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Table 27. Device Number Assignment
GMCH/MCH Function Host-Hub Interface, DDR SDRAM I/F, Legacy control Host-to-AGP Bridge(Virtual PCI-to-PCI) Integrated Graphics Controller (IGD) Bus #0, Device# Device #0 (Intel 852GME GMCH and Intel 852PM MCH) Device #1 (Intel 852GME GMCH and Intel 852PM MCH) Device #2 (Intel 852GME GMCH)
3.2
Nomenclature for Access Attributes
Table 28 provides the nomenclature for the access attributes.
Table 28. Assignment Nomenclature for Access Attributes
RO R/W R/W/L R/WC Read Only. If a register is Read Only, Writes to this register have no effect. Read/Write. A register with this attribute can be Read and Written. Read/Write/Lock. A register with this attribute can be Read, Written, and Locked. Read/Write Clear. A register bit with this attribute can be Read and Written. However, a Write of a 1 clears (sets to 0) the corresponding bit and a Write of a 0 has no effect. Read/Write Once. A register bit with this attribute can be Written to only once after power up. After the first Write, this bit becomes Read Only. Lock. A register bit with this attribute becomes Read Only after a Lock bit is set. Some of the GMCH/MCH registers described in this section contain reserved bits, which are labeled "Reserved." Software must deal correctly with fields that are Reserved. On Reads, software must use appropriate masks to extract the defined bits and not rely on Reserved bits being of any particular value. On Writes, software must ensure that the values of Reserved bit positions are preserved. That is, the values of Reserved bit positions must first be Read, Merged with the new values for other bit positions and then Written back. Note the software does not need to perform Read, Merge, and Write operations for the Configuration Address register. In addition to Reserved bits within a register, the GMCH/MCH contains address locations in the configuration space of the Host-Hub Interface Bridge entity that are marked either "Reserved" or "Intel Reserved." The GMCH/MCH responds to accesses to "Reserved" address locations by completing the Host cycle. When a "Reserved" register location is Read, in certain cases, a zero value can be returned ("Reserved" registers can be 8-bit, 16-bit, or 32-bit in size) or a non-zero value can be returned. In certain cases, Writes to "Reserved" registers may have no effect on the GMCH/MCH or may cause system failure. Registers that are marked as "Intel Reserved" must not be modified by system software. Upon Reset, the GMCH/MCH sets its entire internal configuration registers to predetermined default states. Some register values at Reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DDR SDRAM configurations, operating parameters and optional system features that are applicable, and to program the GMCH/MCH registers accordingly. SW Semaphore.
R/WO L Reserved Bits
Reserved Registers
Default Value upon a Reset
S
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A physical PCI Bus #0 does not exist. The hub interface and the internal devices in the GMCH/MCH and ICH4-M logically constitute PCI Bus #0 to configuration software.
3.3
Standard PCI Bus Configuration Mechanism
The PCI bus defines a slot based "configuration space" that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU. Configuration Space is supported by a mapping mechanism implemented within the GMCH/MCH. The PCI 2.2 specification defines two mechanisms to access Configuration Space: Mechanism #1 and Mechanism #2. The GMCH/MCH support only Mechanism #1. The Configuration Access Mechanism makes use of the CONFIG_ADDRESS register (at I/O address 0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To reference a Configuration register a Dword I/O Write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device, and a specific Configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be a 1 to enable a Configuration cycle. CONFIG_DATA then becomes a window into the four Bytes of Configuration Space specified by the contents of CONFIG_ADDRESS. Any Read or Write to CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate Configuration cycle. The GMCH is responsible for translating and routing the CPU's I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH/MCH Configuration registers, hub interface, or AGP_PCI_B.
3.4
Routing Configuration Accesses
The GMCH/MCH support two bus interfaces: the hub and the AGP/PCI interface. PCI Configuration cycles are selectively routed to this interface. The GMCH/MCH is responsible for routing PCI Configuration cycles to the proper interface. PCI configuration cycles to the ICH4-M internal devices, and Primary PCI (including downstream devices) are routed to the ICH4-M via the hub interface. AGP/PCI_B configuration cycles are routed to AGP. The AGP/PCI_B interface is treated as a separate PCI bus from the configuration point of view. Routing of configuration AGP/PCI_B is controlled via the standard PCI-to-PCI bridge mechanism using information contained within the Primary bus number, the Secondary bus number, and the Subordinate bus number registers of the corresponding PCI-to-PCI bridge device.
3.4.1
PCI Bus #0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, then the Configuration cycle is targeting a PCI bus #0 device.
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Register Description
R
The Host-Hub Interface Bridge entity within the GMCH/MCH is hardwired as Device #0 on PCI Bus #0. The Host-AGP/PCI_B Bridge entity within the GMCH/MCH is hardwired as Device #1 on PCI Bus #0. Configuration cycles to any of the GMCH/MCH's internal devices are confined to the GMCH/MCH and not sent over hub interface. Accesses to disabled GMCH/MCH internal devices will be forwarded over the hub interface as Type 0 Configuration cycles.
3.4.2
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the HostAGP/PCI_B device's Secondary bus number register or greater than the value in the HostAGP/PCI_B device's Subordinate bus number register, the GMCH/MCH will generate a Type 1 Hub interface configuration cycle. A[1:0] of the hub interface request packet for the Type 1 configuration cycle will be "01". This Hub interface configuration cycle will be sent over hub interface. If the cycle is forwarded to the ICH4-M via hub interface, the ICH4-M compares the non-zero Bus Number with the Secondary bus number and Subordinate bus number registers of its PCI-toPCI bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH4M's hub interfaces, or a downstream PCI bus.
3.4.3
AGP/PCI_B Bus Configuration Mechanism
From the chipset configuration perspective, AGP/PCI_B is seen as PCI bus interfaces residing on a Secondary Bus side of the "virtual" PCI-to-PCI bridges referred to as the GMCH/MCH HostPCI_B/AGP bridge. On the Primary bus side, the "virtual" PCI-to-PCI bridge is attached to PCI Bus #0. Therefore the Primary bus number register is hardwired to "0". The "virtual" PCI-to-PCI bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP/PCI_B interface. Type 1 configuration cycles on PCI Bus #0 that have a Bus number that matches the Secondary bus number of the GMCH/MCH's "virtual" Host-to-PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the PCI_B/AGP interface. The GMCH/MCH will decode the Device Number field [15:11] and assert the appropriate GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration mechanism. If the Bus Number is non-zero, greater than the value programmed into the Secondary bus number register, and less than or equal to the value programmed into the Subordinate bus number register, then the configuration cycle is targeting a PCI bus downstream of the targeted interface. The GMCH/MCH will generate a Type 1 PCI configuration cycle on PCI_B/AGP. To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software will go through the following sequence: 1. Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses. 2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process will include the configuration of the "virtual" PCI-to-PCI bridges within the GMCH/MCH used to map the AGP device's address spaces in a software specific manner.
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Register Description
R
Note: Although initial AGP platform implementations will not support hierarchical buses residing below AGP, this specification still must define this capability in order to support PCI-66 compatibility. Note also that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses coming out of the root AGP device.
3.5
Register Definitions
The GMCH/MCH contains four sets of software accessible registers accessed via the Host CPU I/O Address Space, and they are as follows: Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI and AGP Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification. Internal Configuration registers: residing within the GMCH/MCH, they are partitioned into three logical device register sets ("logical" since they reside within the single physical device). * The first register set is dedicated to Host-HI Bridge functionality (i.e. DDR SDRAM configuration, other chip-set operating parameters and optional features). * The second register block is dedicated to Host-AGP/PCI_B Bridge functions (controls AGP/PCI_B interface configurations and operating parameters). * The third register block is for the integrated graphics functions. Internal Memory Mapped Configuration registers: reside in the GMCH/MCH Device #0. Internal Memory Mapped Configuration registers and Legacy VGA registers: reside in the GMCH Device #2 that controls the Integrated Graphics Controller. The GMCH/MCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multibyte numeric fields use "Little Endian Byte Ordering" (i.e., lower addresses contain the least significant parts of the field).
Reserved Bits
Some of the GMCH/MCH registers described in this section contain Reserved bits. These bits are labeled "Reserved". Software must deal correctly with fields that are Reserved. On Reads, software must use appropriate Masks to extract the defined bits and not rely on Reserved bits being any particular value. On Writes, software must ensure that the values of Reserved bit positions are preserved. That is, the values of Reserved bit positions must first be Read, Merged with the new values for other bit positions and then Written back. Note: The software does not need to perform Read, Merge, and Write operations for the Configuration Address register.
Default Value Upon Reset
Upon a Full Reset, the GMCH/MCH set all of its Internal Configuration registers to a predetermined default state. Some register values at Reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the
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Register Description
R
DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH/MCH registers accordingly.
3.6
I/O Mapped Registers
The GMCH/MCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the Configuration Space and determines what portion of Configuration Space is visible through the Configuration Data window.
3.6.1
CONFIG_ADDRESS - Configuration Address Register
I/O Address: Default Value: Access: Size: 0CF8h Accessed as a Dword 00000000h Read/Write 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word reference will "pass through" the Configuration Address register and the hub interface, onto the PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. Figure 4. Configuration Address Register
31 30 0 R
24 23 0
16 15 0
11 10 0
87 0
2 1 0 Bit R Default
Reserved Register Number Function Number Device Number Bus Number Reserved Enable
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Register Description
R
Bit 31
Description Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. Reserved Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration Cycle is a hub interface agent (GMCH, ICH4-M, etc.). The Configuration Cycle is forwarded to hub interface if the Bus Number is programmed to 00h and the GMCH/MCH is not the target (the device number is >= 2).
30:24 23:16
15:11
Device Number: This field selects one agent on the PCI Bus selected by the Bus Number. When the Bus Number field is 00 the GMCH/MCH decode the Device Number field. The GMCH/MCH is always Device #0 for the Host-hub interface bridge entity. Therefore, when the Bus Number =0 and the Device Number=0-1 the internal GMCH/MCH devices are selected. For Bus Numbers resulting in Hub Interface Configuration cycles, the GMCH/MCH propagates the device number field as A[15:11].
10:8
Function Number: This field is mapped to A[10:8] during Hub Interface Configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The GMCH/MCH ignore Configuration cycles to its internal Devices if the function number is not equal to 0. Register Number: This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address register. This field is mapped to A[7:2] during Hub Interface Configuration cycles. Reserved
7:2
1:0
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Register Description
R
3.6.2
CONFIG_DATA - Configuration Data Register
I/O Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write 32 bits
CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Figure 5. Configuration Data Register
31
0
0
Bit Default
Configuration Data Window
Bit 31:0
Description Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to the CONFIG_DATA register will be mapped to Configuration Space using the contents of CONFIG_ADDRESS.
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3.7
Host-Hub Interface Bridge Device Registers (Device #0, Function #0)
Table 29 summarizes the configuration space for Device #0, Function#0.
Table 29. GMCH/MCH Configuration Space - Device #0, Function#0
Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Sub-Class Code Base Class Code Header Type Aperture Base Configuration Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Capability Identification Registers - RCOMP Base Address GMCH Misc. Control GMCH Graphics Control Device and Function Control Fixed Dram Hole Control Programmable Attribute Map Register Symbol VID DID PCICMD PCISTS RID Register Start 00 02 04 06 08 Register End 01 03 05 07 08 Default Value 8086h 3580h 0006h 0090h 01h 02h SUBC BCC HDR APBASE SVID 0A 0B 0E 10 2C 0A 0B 0E 13 2D 00h 06h 80h 08h 0000h RO RO RO R/W, RO R/WO RO RO RO,R/W RO,R/WC RO Access
SID CAPPTR CAPID RRBAR
2E 34 40 48
2F 34 44 4B
0000h 40h Chipset Dependent 0000h
R/WO RO RO R/W, RO
GMC GGC DAFC FDHC PAM (6:0)
50 52 54 58 59
51 53 55 58 5F
0000h 0030h 0000h 00h 00h Each
R/W R/W R/W R/W R/W
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Register Description
R
Register Name System Management RAM Control Extended System Management RAM Control Error Status Error Command SMI Command SCI Command Secondary Host Interface Control Register AGP Capability Identifier AGP Status Register AGP Command AGP Control AGP Functional Aperture Translation Table Base AGP Interface Multi Transaction Timer Low Priority Transaction Timer
Register Symbol SMRAM
Register Start 60
Register End 60
Default Value 02h
Access R/W/L
ESMRAMC
61
61
38h
R/W/L
ERRSTS ERRCMD SMICMD SCICMD SHIC
62 64 66 67 74
63 65 66 67 77
0000h 0000h 00h 00h 00006010h
R/WC R/W R/W R/W RO, R/W
ACAPID AGPSTAT AGPCMD AGPCTRL AFT ATTBASE
A0 A4 A8 B0 B2 B8
A3 A7 AB B1 B3 BB
00200002h 1F000217h 0000 0000h 0000h E9F0h 00000000h
RO RO RO, R/W RO, R/W R/W, R/WC RO, R/W
AMTT
BC
BC
00h
R/W
LPTT
BD
BD
00h
R/W
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Register Description
R
3.7.1
VID - Vendor Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits
The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification (VID): This register field contains the PCI standard identification for Intel = 8086h
3.7.2
DID - Device Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 02-03h 3580h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number (DID): This is a 16-bit value assigned to the GMCH/MCH Host-hub interface bridge, Device #0. = 3580h
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Register Description
R
3.7.3
PCICMD - PCI Command Register (Device #0)
Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits
Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit 15:10 9 Reserved
Description
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes to this bit position have no affect. SERR Enable (SERRE): This bit is a global enable bit for Device #0 SERR messaging. The GMCH/MCH does not have an SERR# signal, but communicates the SERR# condition by sending an SERR message to the ICH4-M. 1 = Enable. GMCH/MCH is enabled to generate SERR messages over hub interface for specific Device #0 error conditions that are individually enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers. 0= SERR message is not generated by the GMCH/MCH for Device #0.
8
NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE bit to control error reporting for error conditions occurring on Device #1. The two control bits are used in a logical OR manner to enable the SERR hub interface message mechanism. 7 6 5 4 Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect. Parity Error Enable (PERRE): PERR# is not implemented by GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect. VGA Palette Snoop Enable (VGASNOOP): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Memory Write and Invalidate Enable (MWIE): The GMCH/MCH will never issue memory write and invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect. Special Cycle Enable (SCE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Bus Master Enable (BME): The GMCH/MCH is always enabled as a master on hub interface. This bit is hardwired to a 1. Writes to this bit position have no effect. Memory Access Enable (MAE): The GMCH/MCH always allows access to main system memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect. I/O Access Enable (IOAE): This bit is not implemented in the GMCH/MCH and is hardwired to a 0. Writes to this bit position have no effect.
3 2 1
0
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Register Description
R
3.7.4
PCI Status Register (Device #0)
Address Offset: Default Value: Access: Size: 06-07h 0090h Read Only, Read/WriteClear 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit 15 14
Description Detected Parity Error (DPE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Signaled System Error (SSE): R/WC. This bit is set to 1 when GMCH Device #0 generates an SERR message over hub interface for any enabled Device #0 error condition. Device #0 error conditions are enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit. Received Master Abort Status (RMAS): R/WC. This bit is set when the GMCH/MCH generates a hub interface request that receives a Master Abort completion packet or Master Abort Special Cycle. Software clears this bit by writing a 1 to it. Received Target Abort Status (RTAS): R/WC. This bit is set when the GMCH/MCH generates a hub interface request that receives a Target Abort completion packet or Target Abort Special Cycle. Software clears this bit by writing a 1 to it. If bit 6 in the ERRCMD is set to a 1 and a Serr# special cycle is generated on the hub interface bus. Signaled Target Abort Status (STAS): The GMCH/MCH will not generate a Target Abort hub interface completion packet or Special Cycle. This bit is not implemented in the GMCH/MCH and is hardwired to a 0. Writes to this bit position have no effect. DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect. Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the GMCH/MCH does not limit optimum DEVSEL timing for PCI_A. Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented by the GMCH/MCH therefore this bit is hardwired to 0. Writes to this bit position have no effect. Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the GMCH/MCH does not limit the optimum setting for PCI_A. Reserved Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. Reserved
13
12
11
10:9
8
7
6:5 4
3:0
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Register Description
R
3.7.5
RID - Revision Identification (Device #0)
Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits
This register contains the revision number of the GMCH/MCH Device #0. These bits are read only and writes to this register have no effect.
Bit 7:0
Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH Device #0. Intel 852GME = 02 Intel 852PM = 02
3.7.6
SUBC - Sub Class Code Register (Device #0)
Address Offset: Default Value: Access: Size: 0Ah 00h Read Only 8 bits
This register contains the Sub-Class Code for the GMCH/MCH Device #0. This code is 00h indicating a Host Bridge device.
Bit 7:0
Description Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the GMCH/MCH falls. The code is 00h indicating a Host Bridge.
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R
3.7.7
BCC - Base Class Code Register (Device #0)
Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits
This register contains the Base Class code of the GMCH/MCH Device #0. This code is 06h indicating a bridge device.
Bit 7:0
Description Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH/MCH. This code has the value 06h, indicating a Bridge device.
3.7.8
HDR - Header Type Register (Device #0)
Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. If Functions other than 0 are disabled, this field returns a 00 to indicate that the GMCH/MCH is a single function device with standard header layout. Writes to this location have no effect.
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Register Description
R
3.7.9
APBASE - Aperture Base Configuration (Device #0)
Address Offset: Default Value: Access: Size: 10h 00000008h Read Only, Read/Write 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to "0" or behave as hardwired to "0"). To allow for flexibility (of the aperture), an additional register called APSIZE controls bits of the APBASE that behave as hardwired to "0" to keep the aperture size aligned. This register is programmed by the GMCH/MCH specific BIOS code before any of the generic configuration software runs. Note: Bit 1 of the register 51h is used to prevent accesses to the aperture range before this register is initialized and the appropriate translation table structure has been established in the main memory.
Bit 31:28
Description Upper Programmable Base Address (UPBITS): Upper Programmable Base Address bits-- R/W. These bits are used to locate the range size selected via lower bits 27:25. Default = 0000 Lower "Hardwired"/Programmable Base Address bits (LOBITS): These bits behave as "hardwired" or as a programmable depending on the contents of the APSIZE register as defined below: 27 r/w r/w 0 26 r/w 0 0 Aperture Size 64 MB 128 MB 256 MB
27:22
Bits 25:22 = 0, enforcing a minimum aperture size to 64 MB. If AGP Capability in CAPREG is intact ("0") then: Bits 27:26 are controlled by the bits 5:4 of the APSIZE register in the following manner: If bit APSIZE[5]=0 then APBASE[27]=0 and if APSIZE[5]=1 then APBASE[27]=r/w (read/write). 21:4 3 Lower Bits (LOWBITS): These bits are 0. Prefetchable (PF): This bit is 1 to identify the Graphics Aperture range as a prefetchable as per the PCI specification for base address registers. This implies that there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables, and the GMCH/MCH may merge processor writes into this range without causing errors. Addressing Type (TYPE): These bits determine addressing type and they are hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space as per the PCI specification for base address registers. Memory Space Indicator (MSPACE): This bit is 0 and is used to identify the aperture range as a memory range as per the specification for PCI base address registers.
2:1
0
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Register Description
R
3.7.10
SVID - Subsystem Vendor Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0
Description Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes Read Only.
3.7.11
SID - Subsystem Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h Read/Write Once 16 bits
This value is used to identify a particular subsystem.
Bit 15:0
Description Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been written once, it becomes Read Only.
3.7.12
CAPPTR - Capabilities Pointer Register (Device #0)
Address Offset: Default Value: Access: Size: 34h 40h Read Only 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list.
Bit 7:0
Description Pointer to the offset of the first capability ID register block: In this case the first capability is the Product-Specific Capability, which is located at offset 40h.
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Register Description
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3.7.13
CAPIDCapability Identification Register (Device #0)
Address Offset: Default: Access: Size 40 - 44h Chipset Dependent Read Only 40 bits
The Capability Identification Register uniquely identifies chipset capabilities as defined in the table below. The bits in this register are intended to define a capability ceiling for each feature, not a capability select. The BIOS must read this register to identify the part and comprehend the capabilities specified within when configuring the effected portions of the GMCH/MCH. The default setting, in most cases, allows the maximum capability. This register is Read Only. Writes to this register have no effect.
Bit 39:37 Capability ID [2:0]: 000-001= Reserved 010 = Intel 852GME GMCH 011 = Intel 852PM MCH 100 = Reserved 101 = Intel 852GM GMCH 110 - 111 = Reserved 36:31 30 Reserved Limit System Memory ECC Capability 0 = ECC capability supported. 1 = ECC capability not supported. 29:28 27:24 23:16 15:0 Reserved
Description
CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG definition. Cap_length: This field has the value 05h indicating the structure length. Reserved
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3.7.14
RRBAR - Register Range Base Address Register (Device #0)
Address Offset: Default Value: Access: Size: 48-4Bh 00000000h Read/Write, Read Only 32 bits
This register requests a 64-kB allocation for the Device registers. The base address is defined by bits 31 to 16 and can be used to access device configuration registers. Only Dword aligned writes are allowed to this space. See Table below for address map within the 64-kB space. This addressing mechanism may be used to write to registers that modify the device address map. However, before using or allowing the use of the modified address map the bios must synchronize using an IO or Read cycle. Bit 8 of the GCC register is used to prevent accesses to this range before the configuration software initializes this register.
Bit 31:16 15:0
Description Memory Base Address--R/W. Set by the OS, these bits correspond to address signals [31:16]. Reserved
Address Range 0000h to FFFFh Space Sub Ranges 0000h to 00FFh 0100h to 01FFh 0200h to 02FFh 0300h to 03FFh 0400h to 07FFh 0800h to 08FFh 0900h to 0FFFh 1000h to 10FFh 1100h to 11FFh 1200h to 7FFFh 8000h to 8FFFh 9000h to FFFFh Description Read/Write (As in Configuration Space): Maps to 00-FFh of Device #0, Function #0 register space. Read/Write (As in Configuration Space): Maps to 00-FFh of Device #0, Function #1 register space. Reserved Read/Write (As in Configuration Space): Maps to 00-FFh of Device #0, Function #3 register space. Reserved Read/Write (As in Configuration Space): Maps to 00-FFh of Device #1, Function #0 register space. Reserved Read/Write (As in Configuration Space): Maps to 00-FFh of Device #2, Function #0 register space. Read/Write (As in Configuration Space): Maps to 00-FFh of Device #2, Function #1 register space. Reserved System memory Rcomp memory Range. Reserved
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Register Description
R
3.7.15
GMC - GMCH Miscellaneous Control Register (Device #0)
Address Offset: Default Value: Access: Size: 50-51h 0000h Read/Write 16 bits
Bit 15:10 9 Reserved
Description
Aperture Access Global Enable--R/W. This bit is used to prevent access to the aperture from any port (CPU, PCI0 or AGP/PCI1) before the aperture range is established and appropriate translation table in the main DDR SDRAM has been initialized. Default is 0. It must be set after system is fully configured for aperture accesses. NOTE: If the AGP_DVO strap is set to DVO then this bit is is RO.
8
RRBAR Access Enable--R/W: 1 = Enables the RRBAR space. 0 = Disable
7:1 0
Reserved MDA Present (MDAP)--R/W: This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to hub interface. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses. MDA resources are defined as the following: Memory: 0B0000h - 0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode) Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to hub interface even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGA 00 01 10 MDA Behavior All References to MDA and VGA go to hub interface (Default) Reserved All References to VGA go to PCI. MDA-only references (I/O address 3BF and aliases) will go to hub interface. VGA References go to PCI; MDA References go to hub interface
11
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Register Description
R
3.7.16
GGC - GMCH Graphics Control Register (Device 0)
Address Offset: Default Value: Access: Size: 52-53h 0030h Read/Write 16 bits
Bit 15:7 6:4 Reserved
Description
Graphics Mode Select (GMS): This field is used to select the amount of main system memory that is pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that system memory is pre-allocated only when Internal Graphics is enabled. 000 = No system memory pre-allocated. Device #2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within Device #2 Function #0 Class Code register is 80.
001 = DVMT (UMA) mode, 1 MB of system memory pre-allocated for frame buffer. 010 = DVMT (UMA) mode, 4 MB of system memory pre-allocated for frame buffer. 011 = DVMT (UMA) mode, 8 MB of system memory pre-allocated for frame buffer. 100 = DVMT (UMA) mode, 16 MB of system memory pre-allocated for frame buffer. 101 = DVMT (UMA) mode, 32 MB of system memory pre-allocated for frame buffer. All other combinations reserved. 3:2 1 Reserved IGD VGA Disable (IVD): 1 = Disable. Device #2 (IGD) does not claim VGA Memory and I/O Mem cycles, and the SubClass Code field within Device #2 Function #0 Class Code register is 80. 0 = Enable. Device #2 (IGD) claims VGA Memory and I/O cycles, the Sub-Class Code within Device #2 Class Code register is 00. 0 Reserved
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Register Description
R
3.7.17
DAFC - Device and Function Control Register (Device 0)
Address Offset: Default Value: Access: Size: 54-55h 0000h Read/Write 16 bits
This 16-bit register controls the visibility of devices and functions within the GMCH/MCH to configuration software.
Bit 15:8 7 Reserved Device #2 Disable: 1 = Disabled. 0 = Enabled. 6:3 2 Reserved Device #0 Function #3 Disable:
Description
1 = Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges. 0 = Enable Function #3 within Device #0. 1 0 Reserved Device #0 Function #1 Disable: 1 = Disable Function #1 within Device #0. 0 = Enable Function #1 within Device #0.
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Register Description
R
3.7.18
FDHC - Fixed DRAM Hole Control Register (Device #0)
Address Offset: Default Value: Access: Size: 58h 00h Read/Write 8 bits
This 8-bit register controls a single fixed DDR SDRAM hole: 15-16 MB.
Bit 7
Description Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles matching an enabled hole are passed onto ICH4-M through hub interface. The GMCH/MCH will ignore hub interface cycles matching an enabled hole. NOTE: A selected hole is not re-mapped. 0 = None 1 = 15 MB-16 MB (1MBs)
6:0
Reserved
3.7.19
PAM(6:0) - Programmable Attribute Map Register (Device #0)
Address Offset: Default Value: Attribute: Size: 59-5Fh 00h Each Read/Write 4 bits/register, 14 registers
The GMCH allows programmable DDR SDRAM attributes on 13 legacy system memory segments of various sizes in the 640 kB -1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6 processor. Two bits are used to specify system memory attributes for each system memory segment. These bits apply to both Host and hub interface initiator accesses to the PAM areas. These attributes are: RE - Read Enable. When RE = 1, the CPU Read accesses to the corresponding system memory segment are claimed by the GMCH/MCH and directed to main system memory. Conversely, when RE = 0, the Host Read accesses are directed to PCI0. WE - Write Enable. When WE = 1, the Host Write accesses to the corresponding system memory segment are claimed by the GMCH/MCH and directed to main system memory. Conversely, when WE = 0, the Host Write accesses are directed to PCI0. The RE and WE attributes permit a system memory segment to be Read Only, Write Only, Read/Write, or Disabled. For example, if a system memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM register controls two regions, typically 16 kB in size. Each of these regions has a 4-bit field. The 4 bits that control each region have the same encoding and are defined in the following table.
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Register Description
R
Table 30. Attribute Bit Assignment
Bits [7, 3] Reserved X Bits [6, 2] Reserved X Bits [5, 1] WE 0 Bits [4, 0] RE 0 Description Disabled. DDR SDRAM is disabled and all accesses are directed to hub interface. The GMCH/MCH does not respond as a hub interface target for any Read or Write access to this area. Read Only. Reads are forwarded to DDR SDRAM and Writes are forwarded to hub interface for termination. This Write protects the corresponding DDR SDRAM segment. The GMCH/MCH will respond as a hub interface target for Read accesses but not for any Write accesses. Write Only. Writes are forwarded to DDR SDRAM and Reads are forwarded to the hub interface for termination. The GMCH/MCH will respond as a hub interface target for Write accesses but not for any Read accesses. Read/Write. This is the normal operating mode of main system memory. Both Read and Write cycles from the host are claimed by the GMCH/MCH and forwarded to DDR SDRAM. The GMCH/MCH will respond as a hub interface target for both Read and Write accesses.
X
X
0
1
X
X
1
0
X
X
1
1
As an example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the system performance. When BIOS is shadowed in main system memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to Write Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the Expansion bus. The Host then does a Write of the same address, which is directed to main system memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read Only so that all Writes are forwarded to the Expansion bus. Figure 6 and Table 36 show the PAM registers and the associated attribute bits.
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Register Description
R
Figure 6. PAM Registers
Offset PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 6 R 5 WE 4 RE 3 R 2 R 1 WE 0 RE Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved
pam
7 R Reserved Reserved
Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W ) 1=Enable 0=Disable
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Register Description
R
Table 31. PAM Registers and Associated System Memory Segments
PAM Reg Attribute Bits System Memory Segment Comments Offset
PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] R R R R R R R R R R R R R R R R R R R R R R R R R R WE WE WE WE WE WE WE WE WE WE WE WE WE
Reserved RE RE RE RE RE RE RE RE RE RE RE RE RE 0F0000h-0FFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh BIOS Area ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension
59h 59h 5Ah 5Ah 5Bh 5Bh 5Ch 5Ch 5Dh 5Dh 5Eh 5Eh 5Fh 5Fh
For details on overall system address mapping scheme see the Address Decoding section of this document.
DOS Application Area (00000h-9FFFh)
The DOS area is 640 kB in size and it is further divided into two parts. The 512-kB area at 0 to 7FFFFh is always mapped to the main system memory controlled by the GMCH/MCH, while the 128-kB address range from 080000 to 09FFFFh can be mapped to PCI0 or to main DDR SDRAM. By default this range is mapped to main system memory and can be declared as a main system memory hole (accesses forwarded to PCI0) via GMCH/MCH's FDHC Configuration register.
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Register Description
R
Video Buffer Area (A0000h-BFFFFh)
Attribute Bits do not control this 128-kB area. The Host-initiated cycles in this region are always forwarded to either PCI0 or PCI2 unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA Control Mechanism of the "Virtual" PCI-PCI Bridge Device embedded within the GMCH. This area can be programmed as SMM area via the SMRAM register. When used as an SMM space, this range can not be accessed from the hub interface.
Expansion Area (C0000h-DFFFFh)
This 128-kB area is divided into eight 16-kB segments that can be assigned with different attributes via PAM Control register as defined in Table 31 and Figure 6.
Extended System BIOS Area (E0000h-EFFFFh)
This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes via PAM Control register as defined in Table 31 and Figure 6.
System BIOS Area (F0000h-FFFFFh)
This area is a single 64-kB segment that can be assigned with different attributes via PAM Control register as defined in Table 31 and Figure 6.
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Register Description
R
3.7.20
SMRAM - System Management RAM Control Register (Device #0)
Address Offset: Default Value: Access: Size: 60h 02h Read/Write/Lock, Read Only 8 bits
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock Bits function only when G_SMRAME Bit is set to a 1. Also, the Open Bit must be Reset before the LOCK Bit is set.
Bit 7 6 Reserved
Description
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DDR SDRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1, D_OPEN is Reset to 0 and becomes Read Only. SMM Space Closed (D_CLS): When D_CLS = 1 SMM Space, DDR SDRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DDR SDRAM. This will allow SMM software to reference "through" SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. D_CLS applies to all SMM spaces (Cseg, Hseg, and Tseg). SMM Space Locked (D_LCK): When D_LCK is set to 1, then D_OPEN is Reset to 0 and D_LCK, D_OPEN, G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ and TSEG_EN become Read Only. D_LCK can be set to 1 via a normal Configuration Space Write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM functions is enabled, providing 128 kB of DDR SDRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit must be set to 1, refer to the section on SMM for more details. Once D_LCK is set, this bit becomes Read Only. Compatible SMM Space Base Segment (C_BASE_SEG)--RO: This field indicates the location of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to hub interface. C_BASE_SEG is hardwired to 010 to indicate that the GMCH supports the SMM space at A0000h-BFFFFh.
5
4
3
2:0
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Register Description
R
3.7.21
ESMRAMC - Extended System Management RAM Control (Device #0)
Address Offset: Default Value: Access: Size: 61h 38h Read/Write/Lock 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB.
Bit 7
Description H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM Memory Space is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to DDR SDRAM address 000A0000h to 000BFFFFh. Once D_LCK is set, this bit becomes Read Only.
6
E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined DDR SDRAM ranges in Extended SMRAM (High system memory and T-segment) while not in SMM Space. It is software's responsibility to clear this bit. The software must Write a 1 to this bit to clear it. SMRAM_Cache (SM_CACHE): GMCH/MCH forces this bit to 1. SMRAM_L1_EN (SM_L1): GMCH/MCH forces this bit to 1. SMRAM_L2_EN (SM_L2): GMCH/MCH forces this bit to 1. Reserved TSEG_EN (T_EN): Enabling of SMRAM Memory (TSEG, 1 Mbytes of additional SMRAM Memory) for Extended SMRAM Space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes Read Only.
5 4 3 2:1 0
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Register Description
R
3.7.22
ERRSTS - Error Status Register (Device #0)
Address Offset: Default Value: Access: Size: 62-63h 0000h Read/Write Clear 16 bits
This register is used to report various error conditions. A SERR or SMI cycle may be generated on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
Bit 15:14 13 12 Reserved
Description
FSB Strobe Glitch Detected (PSBAGL): When this bit is set to 1 the GMCH/MCH has detected a glitch on one of the FSB strobes. Writing a 1 to it clears this bit. GMCH/MCH Software Generated Event for SMI: 1 = This indicates the source of the SMI was a Device #2 Software Event. 0 = Software must Write a 1 to clear this bit.
11
GMCH/MCH Thermal Sensor Event for SMI/SCI/SERR: 1 = Indicates that a GMCH/MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been generated. Note that the status bit is set only if a message is sent based on Thermal event enables in Error Command, SMI Command and SCI Command registers. Note that a Trip Point can generate one of SMI, SCI or SERR interrupts (two or more per event is illegal). Multiple Trip Points can generate the same interrupt. If software chooses this mode, then subsequent Trips may be lost. 0 = Software must Write a 1 to clear this status bit. If this bit is set, then an interrupt message will not be sent on a new Thermal Sensor event.
10 9
Reserved LOCK to non-DDR SDRAM Memory Flag (LCKF)--R/WC: 1 = Indicates that a CPU initiated LOCK cycle targeting non-DDR SDRAM Memory Space occurred. 0 = Software must Write a 1 to clear this status bit
8
Received Refresh Timeout--R/WC: 1 = This bit is set when 1024 memory core refresh are Queued up. 0 = Software must Write a 1 to clear this status bit.
7
DRAM Throttle Flag (DTF)--R/WC: 1 = Indicates that the DDR SDRAM Throttling condition occurred. 0 = Software must Write a 1 to clear this status bit.
6:0
Reserved
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Register Description
R
3.7.23
ERRCMD - Error Command Register (Device #0)
Address Offset: Default Value: Access: Size: 64-65h 0000h Read/Write 16 bits
This register enables various errors to generate. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. It is software's responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.
Bit 15:14 13 12 11 Reserved
Description
SERR on FSB Strobe Glitch: When this bit is asserted, the GMCH/MCH will generate a SERR message when a glitch is detected on one of the FSB strobes. Reserved SERR on GMCH/MCH Thermal Sensor Event: 1 = The GMCH/MCH generates a SERR cycle on a Thermal Sensor Trip that requires an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a Thermal Sensor Trip event. 0 = Software must Write a 1 to clear this status bit.
10 9
Reserved SERR on LOCK to non-DDR SDRAM Memory: 1 = The GMCH/MCH generates an SERR cycle when a CPU initiated LOCK transaction targeting non-DDR SDRAM Memory Space occurs. 0 = Reporting of this condition is disabled.
8
SERR on DDR SDRAM Refresh timeout: 1 = The GMCH/MCH generates an SERR cycle when a DDR SDRAM Refresh timeout occurs. 0 = Reporting of this condition is disabled.
7
SERR on DDR SDRAM Throttle Condition: 1 = The GMCH/MCH generates an SERR cycle when a DDR SDRAM Read or Write Throttle condition occurs. 0 = Reporting of this condition is disabled.
6
SERR on Receiving Target Abort on Hub Interface: 1 = The GMCH/MCH generates an SERR cycle when a GMCH/MCH cycle is terminated with a Target Abort. 0 = Reporting of this condition is disabled.
5
SERR on Receiving Unimplemented Special Cycle Completion Packet: 1 = The GMCH/MCH generates an SERR cycle when a GMCH/MCH initiated request is terminated with a Unimplemented Special cycle completion packet. 0 = Reporting of this condition is disabled.
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Register Description
R
Bit 4:2 1 Reserved SERR on Multiple-bit ECC Error:
Description
1 = For systems that support ECC, this field must be set to 1. 0 = Reserved 0 SERR on Single-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = Reserved
3.7.24
SMICMD - SMI Error Command Register (Device #0)
Address Offset: Default Value: Access: Size: 66h 00h Read/Write 8 bits
This register enables various errors to generate an SMI cycle. When an Error Flag is set in the ERRSTS register, it can generate a SERR or SMI cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. An error can generate one and only one Error cycle. It is software's responsibility to make sure that when an SMI Error Message is enabled for an error condition, SERR, and SCI Error Messages are disabled for that same error condition.
Bit 7:4 3 Reserved
Description
SMI on GMCH/MCH Thermal Sensor Trip: 1 = An SMI Hub Interface Special cycle is generated by GMCH/MCH when the Thermal Sensor Trip requires an SMI. A Thermal Sensor Trip Point cannot generate more than one special cycle.
2 1
Reserved SMI on Multiple-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = Reserved
0
SMI on Single-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = Reserved
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Register Description
R
3.7.25
SCICMD - SCI Error Command Register (Device #0)
Address Offset: Default Value: Access: Size: 67h 00h Read/Write 8 bits
This register enables various errors to generate a SCI cycle. When an Error Flag is set in the ERRSTS register, it can generate a SERR or SMI cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. An error can generate one and only one Error Special cycle. It is software's responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and SMI Error Messages are disabled for that same error condition.
Bit 7:4 3 Reserved
Description
SCI on GMCH/MCH Thermal Sensor Trip: 1 = An SCI Hub Interface Special cycle is generated by GMCH/MCH when the Thermal Sensor Trip requires an SCI. A Thermal Sensor Trip Point cannot generate more than one special cycle.
2 1
Reserved SCI on Multiple-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = For systems that do not support ECC, this field must be 0.
0
SCI on Single-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = For systems that do not support ECC, this field must be 0.
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Register Description
R
3.7.26
SHIC - Secondary Host Interface Control Register (Device #0)
Address Offset: Default Value: Access: Size: 74-77h 00006010h Read Only, Read/Write 32 bits
Bit 31:2 1 Reserved AGP/DVO Mux Strap (Read only):
Description
Specifies the use of AGP bus muxed with DVO. This bit is defined at Reset by a strap on the G_PAR/DVO_DETECT signal. By default the AGP bus pulls this signal high. If AGP capability is disabled, then the AGP pins are dedicated to internal graphics DVO functionality. If AGP capability is available, then based on this strap, the AGP interface is used for AGP functionality or DVO functionality based on this strap. 1 = AGP. 0 = DVO 0 Reserved
3.7.27
ACAPID - AGP Capability Identifier Register (Device #0)
Address Offset: Default Value: Access: Size: A0-A3h 00200002h Read Only 32 bits
This register provides standard identifier for AGP capability.
Bit 31:24 23:20 Reserved
Description
Major AGP Revision Number. These bits provide a major revision number of AGP specification to which this version of GMCH/MCH conforms. These bits are set to the value 0010b to indicate AGP Rev. 2.x. Minor AGP Revision Number. These bits provide a minor revision number of AGP specification to which this version of GMCH/MCH conforms. This is set to 0000b (i.e., implying Rev x.0) Together with major revision number this field identifies GMCH/MCH as an AGP REV 2.0 compliant device.
19:16
15:8
Next Capability Pointer. AGP capability is the last capability described via the capability pointer mechanism and therefore these bits are set to 00h to indicate the end of the capability linked list. AGP Capability ID. This field identifies the linked list item as containing AGP registers. This field has the value 02h as assigned by the PCI SIG.
7:0
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Register Description
R
3.7.28
AGPSTAT - AGP Status Register (Device #0)
Address Offset: Default Value: Access: Size: A4-A7h 1F000217h Read Only 32 bits
This register reports AGP device capability/status.
Bit 31:24
Description Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the GMCH/MCH. Default =1Fh to allow a maximum of 32 outstanding AGP command requests.
23:10 9 8:6 5 4
Reserved Side Band Addressing (SBA). Indicates that the GMCH/MCH supports side band addressing. Reserved Address Support Above 4 GB (4 GB). Indicates that the GMCH/MCH does not support addresses greater than 4 gigabytes. Fast Writes. 1 = The GMCH/MCH supports Fast Writes from the CPU to the AGP master. (Default)
3 2:0
Reserved RATE. After reset the GMCH/MCH reports its data transfer rate capability. Bit 0 identifies if AGP device supports 1X data transfer mode, bit 1 identifies if AGP device supports 2X data transfer mode, bit 2 identifies if AGP device supports 4X data transfer mode. 1X , 2X , and 4X data transfer modes are supported by the GMCH/MCH and therefore this bit field has a Default Value = 111. NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
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Register Description
R
3.7.29
AGPCMD - AGP Command Register (Device #0)
Address Offset: Default Value: Access: Size: A8-ABh 00000000h Read/Write 32 bits
This register provides control of the AGP operational parameters.
Bit 31:10 9 8 Reserved
Description
Side Band Addressing Enable (SBA_EN). When this bit is set to 1, the side band addressing mechanism is enabled. AGP Enable. 0 = Disable. When this bit is reset to 0, the GMCH/MCH will ignore all AGP operations, including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even if this bit is reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode, the command will be issued. 1 = Enable. The GMCH/MCH will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1.
7:6 5 4
Reserved Address Support Above 4 GB Enable (4 GB_EN). The GMCH/MCH as an AGP target does not support addressing greater than 4 gigabytes. Fast Write Enable. 1 = Enable. GMCH/MCH AGP master supports Fast Writes. 0 = Disable (Default). Fast Writes are disabled.
3 2:0
Reserved Data Rate. The settings of these bits determine the AGP data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. Bit 0: 1X, Bit 1: 2X, Bit 2: 4X. The same bit must be set on both master and target. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space.) NOTE: The selected data transfer mode applies to both AD bus and SBA bus.
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Register Description
R
3.7.30
AGPCTRL - AGP Control Register (Device #0)
Address Offset: Default Value: Access: Size: B0-B1h 0000h Read/Write 16 bits
This register provides for additional control of the AGP interface. Note: Bit 7 is visible to the operating system and must be retained in this position.
Bit 15:8 7 Reserved
Description
GTLB Enable (and GTLB Flush Control). NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs). This bit must not be changed through memory mapped configuration register access space.
6:0
Reserved
3.7.31
AFT - AGP Functional Register (Device #0)
Address Offset: Default Value: Access: Size: B2-B3h E9F0h Read/Write, Read/WriteClear 16 bits
This register provides for additional control of the AGP interface.
Bit 15:11 10 Reserved
Description
PCI Write Streaming Disable (PCIBWSD): When this bit is set to `1', PCI_B writes to DDR SDRAM are disconnected at a 32 byte cache line boundary (write streaming is disabled). When this bit is set to `0' (default), write streaming is enabled. Reserved
9:0
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Register Description
R
3.7.32
APSIZE - Aperture Size (Device #0)
Address Offset: Default Value: Access: Size: B4h 00h Read/Write 8 bits
This register determines the effective size of the Graphics Aperture used for a particular GMCH/MCH configuration. This register can be updated by the GMCH/MCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence. If the register is not updated then a default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications and therefore these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software.
Bit 7:6 5:0 Reserved
Description
Graphics Aperture Size (APSIZE). Each bit in APSIZE[5:4] operates on similarly ordered bits in APBASE[27:26] of the Aperture Base configuration register. When a particular bit of this field is "0" it forces the similarly ordered bit in APBASE[27:26] to behave as "0". When a particular bit of this field is set to "1" it allows corresponding bit of the APBASE[27:26] to be read/write accessible. Only the following combinations are allowed when the Aperture is enabled: Bits[5:4] Aperture Size 11 10 00 64 MB 128 MB 256 MB
Default for APSIZE[5:4]=00b forces default APBASE[27:26] =00b (i.e. all bits respond as "hardwired" to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:4]=11b enables APBASE[27:26] as read/write programmable providing a minimum size of 64 MB. 3:0: Reserved set to zero for software compatibility.
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Register Description
R
3.7.33
ATTBASE - Aperture Translation Table Base Register (Device #0)
Address Offset: Default Value: Access: Size: B8-BBh 00000000h Read/Write 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DDR SDRAM. This value is used by the GMCH/MCH's Graphics Aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical DDR SDRAM address. The ATTBASE register may be dynamically changed. Note: The address provided via ATTBASE is 4 kB aligned.
Bit 31:12 11:0
Description This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. Reserved
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Register Description
R
3.7.34
AMTT - AGP Interface Multi-Transaction Timer Register (Device #0)
Address Offset: Default Value: Access: Size: BCh 00h Read/Write 8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH/MCH's arbiter allows AGP/PCI master to perform multiple back-to-back transactions. The GMCH/MCH's AMTT mechanism is used to optimize the performance of the AGP master (using PCI semantics) that performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). The AMTT mechanism applies to the CPU-AGP/PCI transactions as well and it guarantees to the CPU a fair share of the AGP/PCI interface bandwidth. The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66- MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables this function. The AMTT value can be programmed with 8 clock granularity. For example, if the AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66 MHz) clocks.
Bit 7:3
Description Multi-Transaction Timer Count Value. The number programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current agent (either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. Reserved
2:0
102
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Register Description
R
3.7.35
LPTT - Low Priority Transaction Timer Register (Device #0)
Address Offset: Default Value: Access: Size: BDh 00h Read/Write 8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request. The LPTT does not apply in the case of high-priority request where ownership is transferred directly to high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT value can be programmed with 8 clock granularity. For example, if the LPTT is programmed to 10h, then the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
Bit 7:3
Description Low Priority Transaction Timer Count Value. The number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. Reserved.
2:0
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Register Description
R
3.8
Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)
The following table shows the GMCH/MCH Configuration Space for Device #0, Function #1.
Table 32. Host-Hub interface Bridge/System Memory Controller Configuration Space (Device #0, Function#1)
Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Sub-Class Code Base Class Code Header Type Subsystem Vendor Identification Subsystem Identification Capabilities Pointer DRAM Row 0-3 Boundary DRAM Row 0-3 Attribute DRAM Timing DRAM Controller Power Management Control Dram Controller Mode DRAM Throttle Control Register Symbol VID DID PCICMD PCISTS RID SUBC BCC HDR SVID SID CAPPTR DRB DRA DRT PWRMG DRC DTC Register Start 00 02 04 06 08 0A 0B 0E 2C 2E 34 40 50 60 68 70 A0 Register End 01 03 05 07 08 0A 0B 0E 2D 2F 34 43 51 63 6B 73 A3 Default Value 8086h 3584h 0006h 0080h 02h) 80h 08h 80h 0000h 0000h 00h 00000000h 7777h 18004425h 00000000h 00000081h 00000000h Access RO RO RO,R/W RO,R/WC RO RO RO RO R/WO R/WO RO RW RW RW R/W R/W R/W/L
104
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Register Description
R
3.8.1
VID - Vendor Identification Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits
The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
3.8.2
DID - Device Identification Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 02-03h 3584h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number (DID): This is a 16-bit value assigned to the GMCH/MCH Host- hub interface Bridge Function #1 (3584h).
Datasheet
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Register Description
R
3.8.3
PCICMD - PCI Command Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits
Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
Bit 15:10 9 Reserved
Description
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes to this bit position have no affect. SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect. Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect. Parity Error Enable (PERRE): PERR# is not implemented by GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect. VGA Palette Snoop Enable (VGASNOOP): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Memory Write and Invalidate Enable (MWIE): The GMCH/MCH will never issue Memory Write and Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect. Special Cycle Enable (SCE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Bus Master Enable (BME): The GMCH/MCH is always enabled as a master on hub interface. This bit is hardwired to a 1. Writes to this bit position have no effect. Memory Access Enable (MAE): The GMCH/MCH always allows access to main system memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect. I/O Access Enable (IOAE): This bit is not implemented in the GMCH/MCH and is hardwired to a 0. Writes to this bit position have no effect.
8 7
6 5 4
3 2 1
0
106
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Register Description
R
3.8.4
PCISTS - PCI Status Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 06-07h 0080h Read Only, Read/WriteClear 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
Bit 15 14 13 12 11 10:9
Description Detected Parity Error (DPE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Signaled System Error (SSE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Received Master Abort Status (RMAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Received Target Abort Status (RTAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Signaled Target Abort Status (STAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect. Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the GMCH/MCH does not limit optimum DEVSEL timing for PCI_A. Master Data Parity Error Detected (DPD): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the GMCH/MCH does not limit the optimum setting for PCI_A. Reserved Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that this device/function does not implement new capabilities. Default Value = 0
8 7
6:5 4
3:0
Reserved
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Register Description
R
3.8.5
RID - Revision Identification Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits
This register contains the revision number of the GMCH/MCH Device #0. These bits are Read Only and Writes to this register have no effect.
Bit 7:0
Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH Device #0. Intel 852GME = 02 Intel 852PM = 02
3.8.6
SUBC - Sub-Class Code Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 0Ah 80h Read Only 8 bits
This register contains the Sub-Class code for the GMCH/MCH Device #0. This code is 80h indicating Other Peripheral device.
Bit 7:0
Description Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Peripheral device into which the GMCH/MCH Function #1 falls. The code is 80h indicating Other Peripheral device.
3.8.7
BCC - Base Class Code Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 0Bh 08h Read Only 8 bits
This register contains the Base Class code of the GMCH/MCH Device #0 Function #1. This code is 08h indicating Other Peripheral device.
Bit 7:0
Description Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH/MCH. This code has the value 08h, indicating Other Peripheral device.
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Register Description
R
3.8.8
HDR - Header Type Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. Reads and Writes to this location have no effect.
3.8.9
SVID - Subsystem Vendor Identification Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0
Description Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes Read Only.
3.8.10
SID - Subsystem Identification Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h Read/Write Once 16 bits
This value is used to identify a particular subsystem.
Bit 15:0
Description Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been Written once, it becomes Read Only.
Datasheet
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Register Description
R
3.8.11
CAPPTR - Capabilities Pointer Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list.
Bit 7:0
Description Pointer to the offset of the first capability ID register block: In this case there are no capabilities, therefore these bits are hardwired to 00h to indicate the end of the capability linked list.
3.8.12
DRB - DRAM Row (0:3) Boundary Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 40-43h 00h each Read/Write 8 bits each
The DDR SDRAM Row Boundary Register defines the upper boundary address of each DDR SDRAM row with a granularity of 32-MB. Each row has its own single-byte DRB register. For example, a value of 1 in DRB0 indicates that 32-MB of DDR SDRAM has been populated in the first row. Since the GMCH/MCH supports a total of four rows of system memory, DRB0-3 are used. The registers from 44h-4Fh are reserved for DRBs 4-15. Row0: 40h Row1: 41h Row2: 42h Row3: 43h 44h to 4Fh is reserved. DRB0 DRB1 DRB2 DRB3 = Total System Memory in Row0 (in 32 -MB increments) = Total System Memory in Row0 + Row1 (in 32 -MB increments) = Total System Memory in Row0 + Row1 + Row2 (in 32 -MB increments) = Total System Memory in Row0 + Row1 + Row2 + Row3 (in 32- MB increments)
Each Row is represented by a Byte. Each Byte has the following format.
Bit 7:0 Description DDR SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each DDR SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper address limit of a particular row. Also the minimum system memory supported is 64-MB in 64-Mb granularity; hence bit 0 of this register must be programmed to a zero.
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Register Description
R
3.8.13
DRA - DRAM Row Attribute Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 50-51h 77h Each Read/Write 8 bits
The DDR SDRAM Row Attribute register defines the page sizes to be used when accessing different pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of rows: Row0, 1: 50h Row2, 3: 51h 52h-5Fh: Reserved.
7 R 6 Row attribute for Row1 4 3 R 2 Row Attribute for Row0 0
Bit 7 6:4 Reserved
Description
Row Attribute for odd-numbered Row: This field defines the page size of the corresponding row. 000: Reserved 001: 4 kB 010: 8 kB 011: 16 kB 111: Not Populated Others: Reserved
3 2:0
Reserved Row Attribute for even-numbered Row: This field defines the page size of the corresponding row. 000: Reserved 001: 4 kB 010: 8 kB 011: 16 kB 111: Not Populated Others: Reserved
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Register Description
R
3.8.14
DRT - DRAM Timing Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 60-63h 18004425h Read/Write 32 bits
This register controls the timing of the DDR SDRAM controller.
Bit 31
Description DDR Internal Write to Read Command delay (tWTR): The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5. The tWTR is used to time RD command after a WR command (to same Row): 0: tWTR is set to 1 Clock (CK), used for DDR SDRAM CL=2 or 2.5 1: Reserved
30
DDR SDRAM Write Recovery time (tWR): Write recovery time is a std. DDR SDRAM timing parameter with the value of 15 ns. It should be set to 2 CK when DDR200 is used. The tWR is used to time PRE command launch after a WR command, when DDR SDRAM components are populated. 0: tWR is set to 2 Clocks (CK) 1: tWR is set to 3 Clocks (CK)
29:28
Back To Back Write-Read commands spacing (DDR different Rows/Bank): This field determines the WR-RD command spacing, in terms of common clocks for DDR SDRAM based on the following formula: DQSS + 0.5xBL + TA (WR-RD) - CL DQSS: is time from Write command to data and is always 1 CK BL: is Burst Length and can be set to 4 (using integrated graphics) or 8 (using AGP port) TA (WR-RD): is required DQ turn-around, can be set to 1 or 2 CK CL: is CAS Latency, can be set to 2 or 2.5 Examples of usage: For BL=4, with single DQ turn-around and CL=2, this field must be set to 2 CK (1+2+1-2) Encoding CK between WR and RD commands BL=4 00: 01: 10: 11: 4 3 2 Reserved BL=8 6 5 4
NOTE: This turn around control is used for DDR SDRAM parts only, for all cycle lengths. This field specifies timing for Write-Read commands to different rows. The bigger turnaround value is used in large configurations, where the difference in total channel delay between the fastest and slowest S0-DIMM is larger. It must be used for all configurations, so that read preamble (at maximum corner) will not overlap the previous write data.
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Register Description
R
Bit 27:26
Description Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.5xBL + TA (RD-WR) - DQSS DQSS: is time from Write command to data and is always 1 CK BL: is Burst Length which is set to 4 or 8. TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK CL: is CAS latency, can be set to 2 or 2.5 Examples of usage: For BL=4, with single DQ turn-around and CL=2, this field must be set to 4 CK (2+2+1-1) For BL=8, with single DQ turn-around and CL=2.5, this field must be set to 8 CK (2.5+4+2-1) Encoding CK between RD and WR commands BL = 4 00: 01: 10: 11: 7 6 5 4 BL=8 9 8 7 6
NOTE: Since reads in DDR SDRAM cannot be terminated by Writes, the Space between commands is not a function of Cycle Length but of Burst Length. 25 Back To Back Read-Read commands spacing (DDR, different Rows): This field determines the RD-RD Command Spacing, in terms of common clocks based on the following formula: 0.5xBL + TA(RD-RD) BL: is Burst Length and can be set to 4 or 8. TA (RD-RD): is required DQ turn-around, can be set to 1 or 2 CK Examples of usage: For BL=4, with single DQ turn-around, this field must be set to 3 CK (2+1) For BL=8, with single DQ turn-around, this field must be set to 6 CK (4+2) Encoding CK between RD and RD commands BL = 4 0: 1: 4 3 BL = 8 6 for 2 TA (Read-Read) 5 for 1 TA (Read-Read)
NOTE: Since a Read to a different row does not terminate a Read, the Space between commands is not a function of Cycle Length but of Burst Length. 24:15 Reserved
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Register Description
R
Bit 14:12 Refresh Cycle Time (tRFC):
Description
Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR SDRAM. Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this field will be set to 8 clocks for DDR200, 10 clocks for DDR266. Encoding 000: 001: 010: 011: 100: 101: 110: 111: 11 tRFC 14 13 12 11 10 9 8 7 clocks clocks clocks clocks clocks clocks clocks clocks
Activate to Precharge delay (tRAS), MAX: This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After this time period, the system memory Controller will guarantee to pre-charge the bank. Note that this time period may or may not be set to overlap with time period that requires a refresh to happen. The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank. With a maximum of four rows and four banks per row, there are 16 counters. 0: 120 micro-seconds 1: Reserved.
10:9
Activate to Precharge delay (tRAS), MIN: This bit controls the number of DDR SDRAM clocks for tRAS MIN 00: 8 Clocks 01: 7 Clocks 10: 6 Clocks 11: 5 Clocks
8:7 6:5
Reserved CAS# Latency (tCL): Encoding 00: 01: 10: 11: DDR SDRAM CL 2.5 2 Reserved Reserved
4
Reserved
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Register Description
R
Bit 3:2
Description DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a Row Activate command and a Read or Write command to that row. Encoding 00: 01: 10: 11: tRCD 4 DDR SDRAM Clocks (DDR 333 SDRAM) 3 DDR SDRAM Clocks 2 DDR SDRAM Clocks Reserved
1:0
DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row. Encoding 00: 01: 10: 11: tRP 4 DDR SDRAM Clocks (DDR 333 SDRAM) 3 DDR SDRAM Clocks 2 DDR SDRAM Clocks Reserved
Datasheet
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Register Description
R
3.8.15
PWRMG - DRAM Controller Power Management Control Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 68h-6Bh 00000000h Read/Write 32 bits
Bit 31:24 23:20 Reserved
Description
Row State Control: This field determines the number of clocks the system memory controller will remain in the idle state before it begins pre-charging all pages or powering down rows. - PDEn: Power Down Enable - PCEn: Page Close Enable - TC: Timer Control PDEn(23): 0 0 1 1 1 PCEn(22): 0 1 0 1 1 TC(21:20) XX XX XX 00 01 10 11 Function All Disabled Reserved Reserved Immediate Precharge and Powerdown Reserved Precharge and Power Down after 16 DDR Precharge and Power Down after 64 DDR
1 1 SDRAM Clocks 1 1 SDRAM Clocks 19:17 16 Reserved
SO-DIMM Clock Gating Disable - R/W 0 = Only populated DIMMs received the clock. 1 = The DRAM interface controller will allow all SO-DIMM clocks to toggle.
15
Self Refresh GMCH Memory Interface Data Bus Power Management Optimization Enable: 0 = Enable 1 = Disable
14
CS# Signal Drive Control: 0 = Enable CS# Drive Control, based on rules described in DRC bit 12. 1 = Disable CS# Drive Control, based on rules described in DRC bit 12.
13
Self Refresh GMCH Memory Interface Data Bus Power Management: 0 = In Self Refresh Mode GMCH Power Management is Enabled. 1 = In Self Refresh Mode the GMCH Power Management is Disabled.
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Register Description
R
Bit 12
Description Dynamic Memory Interface Power Management: 0 = Dynamic Memory Interface Power Management Enabled. 1 = Dynamic Memory Interface Power Management Disabled.
11
Rcven DLL shutdown disable: 0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated. 1 = Reserved
10
ECC SO-DIMM Clock tri-state Disable: 0 = When DDR SDRAM ECC is not enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are tri- stated. 1 = When DDR SDRAM ECC is enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are treated just like the other clocks.
9:1 0
Reserved Power State S1/S3 Refresh Control: 0 = Normal Operation, Pending refreshes are not completed before entering Self Refresh for S1/S3. 1 = All Pending Refreshes plus one extra is performed before entering Self Refresh for S1/S3.
Datasheet
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Register Description
R
3.8.16
DRC - DRAM Controller Mode Register (Device #0, Function #1)
Address Offset: Default Value: Access: Size: 70-73h 00000081h RO, Read/Write 32 bits
Bit 31:30
Description Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register definition (Read Only). Initialization Complete (IC): This bit is used for communication of software state between the Memory Controller and the BIOS. BIOS sets this bit to 1 after initialization of the DDR SDRAM Memory Array is complete. Setting this bit to a 1 enables DDR SDRAM Refreshes. On power up and S3 exit, the BIOS initializes the DDR SDRAM array and sets this bit to a 1. This bit works in combination with the RMS bits in controlling Refresh state: IC 0 1 Refresh State OFF ON
29
28:24 23:22
Reserved Number of Channels (CHAN): Reflects that GMCH supports only one system memory channel. 00 Others: One channel is populated appropriately Reserved
21:20
DDIM DDR SDRAM Data Integrity Mode: 00: No-ECC. No read-merge-write on partial writes. ECC data sense-amps are disabled and the data output is tristated (Default). 01: ECC XX: Reserved
19:16 15
Reserved RAS Lock-Out Enable: Set to a 1 if all populated rows support RAS Lock-Out. Defaults to 0. If this bit is set to a 1 the DDR SDRAM Controller assumes that the DDR SDRAM guarantees tRAS min before an auto precharge (AP) completes (Note: An AP is sent with a Read or a Write command). Also, the DDR SDRAM Controller does not issue an activate command to the auto pre-charged bank for tRP. If this bit is set to a 0 the DDR SDRAM Controller does not schedule an AP if tRAS min is not met.
14:13 12
Reserved Address Tri-state enable (ADRTRIEN): When set to a 1, the SDRAM Controller will tri-state the MA, CMD, and CS# (only when all CKEs are deasserted). Note that when CKE to a row is deasserted, fast chip select assertion is not permitted by the hardware. CKEs deassert based on Idle Timer and/or max row count control. 0:- Address Tri-state Disabled 1:- Address Tri-state Enabled
11:10
Reserved
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Register Description
R
Bit 9:7
Description Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate Refreshes will be executed. 000: 001: 010: 011: 111: Other: Refresh disabled Refresh enabled. Refresh interval 15.6 sec Refresh enabled. Refresh interval 7.8 sec Reserved. Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Reserved
Any change in the programming of this field Resets the Refresh counter to zero. This function is for testing purposes, it allows test program to align refresh events with the test and thus improve failure repeatability.
Datasheet
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Register Description
R
Bit 6:4
Description Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special modes are intended for initialization at power up. 000: Post Reset State - When the GMCH exits Reset (power-up or otherwise), the mode select field is cleared to 000. Software is not expected to Write this value, however if this value is Written, there are no side effects (no Self Refresh or any other special DDR SDRAM cycle). During any Reset sequence, while power is applied and Reset is active, the GMCH deasserts all CKE signals. After internal Reset is deasserted, CKE signals remain deasserted until this field is written to a value different than 000. On this event, all CKE signals are asserted. During Suspend (S3, S4), GMCH internal signal triggers DDR SDRAM Controller to flush pending commands and enter all rows into Self-Refresh mode. As part of Resume sequence, GMCH will be Reset, which will clear this bit field to 000 and maintain CKE signals deasserted. After internal Reset is deasserted, CKE signals remain deasserted until this field is Written to a value different than 000. On this event, all CKE signals are asserted. During Entry to other low power states (C3, S1-M), GMCH internal signal triggers DDR SDRAM Controller to flush pending commands and enter all rows in S1 and relevant rows in C3 (Based on RPDNC3) into Self-Refresh mode. During exit to Normal mode, the GMCH signal triggers DDR SDRAM Controller to Exit Self-Refresh and Resume Normal operation without S/W involvement. 001: NOP Command Enable - All CPU cycles to DDR SDRAM result in a NOP command on the DDR SDRAM interface. 010: All Banks Pre-charge Enable - All CPU cycles to DDR SDRAM result in an All Banks Precharge command on the DDR SDRAM interface. 011: Mode Register Set Enable - All CPU cycles to DDR SDRAM result in a Mode Register set command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to Memory address SMA[11,9:0]. SMA3 must be driven to 1 for interleave wrap type. For Double Data Rate MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field. CAS Latency 1.5 Clocks 2.0 Clocks 2.5 Clocks MA[6:4] 001 010 110
SMA[7] should always be driven to a 0. SMA[8] Should be driven to a 1 for DLL Reset and 1 for Normal Operation. SMA[12:9] must be driven to 00000. BIOS must calculate and drive the correct host address for each row of Memory such that the correct command is driven on the SMA[12:0] lines. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1]; BIOS must account for this. 100: Extended Mode Register Set Enable - All CPU cycles to DDR SDRAM result in an "Extended Mode register set" command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines in order to specify the command sent. Host address lines are mapped to DDR SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to Memory address SMA[11,9:0]. SMA[0] = 0 for DLL enable and 1 for DLL disable. All the other SMA lines are driven to 0's. Note that SMAB[5,4,2,1]# are inverted from SMA[5,4,2,1]; BIOS must account for this. 101: Reserved 110: CBR Refresh Enable - In this mode all CPU cycles to DDR SDRAM result in a CBR cycle on the DDR SDRAM interface 111: Normal operation
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Register Description
R
Bit 3 2 Reserved DDR SDRAM Burst Length:
Description
This bit is used to select the DDR SDRAM controller's Burst Length operation mode. It must be set consistently to the DDR SDRAM component setting. Can be set to 8 in DDR SDRAM mode only. Encoding: 0: Burst Length of 4 1: Burst Length of 8 1 Reserved
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Register Description
R
3.8.17
DTC - DRAM Throttling Control Register (Device #0, Function #1)
Offset Address: Default Value: Access: Size: A0-A3h 00000000h Read/Write/Lock 32 bits
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips. Read and Write Bandwidth is measured independently for each bank. If the number of Octal Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM Sampling Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR SDRAM Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower bandwidth checked over smaller time windows. The throttling will be active for the remainder of the current GDSW and for the next GDSW after which it will return to Non-Throttling mode. The throttling mechanism accounts for the actual bandwidth consumed during the sampling window, by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth consumed during the sampling period. Although bandwidth from/to independent rows and GMCH Write bandwidth is measured independently, once Tripped all transactions except high priority graphics Reads are subject to throttling.
Bit 31:28
Description DDR SDRAM Throttle Mode (TMODE): Four bits control which mechanisms for Throttling are enabled in an "OR" fashion. Counter-based Throttling is lower priority than Thermal Trips Throttling when both are enabled and Tripped. Counter-based trips point Throttling values and Thermal-based Trip Point Throttling values are specified in this register. 0000 = Throttling turned off. This is the default setting. All Counters are off.
0001 = Only GMCH Thermal Sensor based Throttling is enabled. If GMCH Thermal Sensor is Tripped, Write Throttling begins based on the setting in WTTC. 0010 = Only Rank Thermal Sensor based Throttling is enabled. When the external SO-DIMM Thermal sensor is Tripped, DDR SDRAM Throttling begins based on the setting in RTTC. 0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTTC. If the GMCH Thermal Sensor is Tripped, Write Throttling begins based on the setting in WTTC. 0100 = Only the GMCH Write Counter mechanism is enabled. When the threshold set in the GDT field is reached, DDR SDRAM Throttling begins based on the setting in WCTC. 0101 = GMCH Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM Throttling begins based on the setting in WCTC. If the GMCH Thermal Sensor is tripped, DDR SDRAM Throttling begins based on the setting in WTTC. If both threshold mechanisms are tripped, the DDR SDRAM Throttling begins based on the settings in WTTC. 0110 = Rank Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms are both enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM Throttling begins based on setting in WCTC. If the external SODIMM Thermal Sensor is tripped, Rank DDR SDRAM throttling begins based on the setting in RTTC.
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Register Description
R
Bit
Description 0111 = Similar to 0101 for Writes and when the Rank Thermal Sensor is tripped, DDR SDRAM Throttling begins based on the setting in RTTC. 1000 = Only Rank Counter mechanism is enabled. When the threshold set in the GDT field is reached, DDR SDRAM Throttling begins based on the setting in RCTC. 1001 = Rank Counter mechanism is enabled and GMCH Thermal Sensor based throttling are both enabled. If GMCH Thermal Sensor is tripped, Write Throttling begins based on the setting in WTTC. When the threshold set in the GDT field is reached, DDR SDRAM Throttling begins based on the setting in RCTC. 1010 = Rank Thermal Sensor and Rank DDR SDRAM Counter mechanisms are both enabled. If the rank DDR SDRAM Counter mechanism threshold is reached, DDR SDRAM Throttling begins based on the setting in RCTC. If the external SO-DIMM Thermal Sensor is tripped, DRAM Throttling begins based on the setting in RTTC. 1011 = Similar to 1010 and if the GMCH Thermal Sensor is tripped, Write Throttling begins based on the setting in WTTC. 1111 = Rank and GMCH Thermal Sensor based Throttling and Rank and GMCH Write Counter based Throttling are enabled. If both the Write Counter and GMCH Thermal Sensor based mechanisms are tripped, DDR SDRAM Throttling begins based on the setting allowed in WTTC. If both the Rank Counter and Rank Thermal Sensor based mechanisms are tripped, DDR SDRAM Throttling begins based on the setting allowed in RTTC.
27:24
Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power Throttle Bandwidth Limits for Read operations to system memory. R/W, RO if Throttle Lock. 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved
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Register Description
R
Bit 23:20
Description Write Counter Based Power Throttle Control (WCTC): These bits select the counter based Power Throttle Bandwidth Limits for Write operations to system memory. R/W, RO if Throttle Lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved
19:16
Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor based Power Throttle Bandwidth Limits for Read operations to system memory. R/W, RO if Throttle Lock. 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved
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Register Description
R
Bit 15:12
Description Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power Throttle Bandwidth Limits for Write operations to system memory. R/W, RO if Throttle Lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved
11
Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0. Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only. Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM Throttling Control register. This bit defaults to 0. Once a 1 is written to this bit, all of the Configuration register bits in DTC (including TTLOCK) except CTLOCK, RCTC and WCTC become Read-Only. Thermal Power Throttle Control fields Enable: 0 = RTTC and WTTC are not used. RCTC and WTCT are used for both Counter and Thermal based Throttling. 1 = RTTC and WTTC are used for Thermal based Throttling.
10
9
8
High Priority Stream Throttling Enable: Normally High Priority Streams are not Throttled when either the counter based mechanism or Thermal Sensor mechanism demands Throttling. 0 = Normal operation. 1 = Block High priority streams during Throttling.
7:0
Global DDR SDRAM Sampling Window (GDSW): This 8-bit value is multiplied by 4 to define the length of time in milliseconds (0-1020) over which the number of Octal Words (16 bytes) Read/Written is counted and Throttling is imposed. Note that programming this field to 00h disables system memory throttling. Recommended values are between 0.25 and 0.75 seconds.
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Register Description
R
3.9
Configuration Process Registers (Device #0, Function #3)
Table 33 summarizes all Device#0, Function #3 registers.
Table 33. Configuration Process Configuration Space (Device#0, Function #3)
Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Sub-Class Code Base Class Code Header Type Subsystem Vendor Identification Subsystem Identification Capabilities Pointer Strap Status HPLL Clock Control Register Symbol VID DID PCICMD PCISTS RID Register Start 00 02 04 06 08 Register End 01 03 05 07 08 Default Value 8086h 3585h 0006h 0080h 01h 02h SUBC BCC HDR SVID 0A 0B 0E 2C 0A 0B 0E 2D 80h 08h 80h 0000h RO RO RO R/WO Access RO RO RO,R/W RO,R/WC RO
SID CAPPTR STRAP HPLLCC
2E 34 A8 C0
2F 34 AB C1
0000h 00h
R/WO RO RO
00h
RO
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Register Description
R
3.9.1
VID - Vendor Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification (VID): This register field contains the PCI standard identification for 8086h.
3.9.2
DID - Device Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 02-03h 3585h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number (DID): This is a 16-bit value assigned to the GMCH/MCH Host-Hub Interface Bridge Function #3 (3585h).
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Register Description
R
3.9.3
PCICMD - PCI Command Register (Device #0)
Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits
Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
Bit 15:10 9 Reserved
Description
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes to this bit position have no effect. SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect. Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect. Parity Error Enable (PERRE): PERR# is not implemented by GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect. VGA Palette Snoop Enable (VGASNOOP): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Memory Write and Invalidate Enable (MWIE): The GMCH/MCH will never issue Memory Write and Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect. Special Cycle Enable (SCE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Bus Master Enable (BME): The GMCH/MCH is always enabled as a master on hub interface. This bit is hardwired to a 1. Writes to this bit position have no effect. Memory Access Enable (MAE): The GMCH/MCH always allows access to Main Memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect. I/O Access Enable (IOAE): This bit is not implemented in the GMCH/MCH and is hardwired to a 0. Writes to this bit position have no effect.
8 7
6 5 4
3 2 1
0
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Register Description
R
3.9.4
PCISTS - PCI Status Register (Device #0)
Address Offset: Default Value: Access: Size: 06-07h 0080h Read Only, Read/WriteClear 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit 15 14 13 12 11 10:9
Description Detected Parity Error (DPE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Signaled System Error (SSE): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Received Master Abort Status (RMAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Received Target Abort Status (RTAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Signaled Target Abort Status (STAS): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit positions have no affect. Device #0 does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that the GMCH/MCH does not limit optimum DEVSEL timing for PCI_A. Master Data Parity Error Detected (DPD): The GMCH/MCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability) so that the GMCH does not limit the optimum setting for PCI_A. Reserved Capability List (CLIST): This bit is hardwired to 0 to indicate to the configuration software that this device/function does not implement new capabilities. Reserved
8 7
6:5 4 3:0
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Register Description
R
3.9.5
RID - Revision Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits
This register contains the revision number of the GMCH/MCH. These bits are Read Only; Writes to this register have no effect.
Bit 7:0
Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH. Intel 852GME = 02 Intel 852PM = 02
3.9.6
SUBC - Sub-Class Code Register (Device #0)
Address Offset: Default Value: Access: Size: 0Ah 80h Read Only 8 bits
This register contains the Sub-Class Code for the GMCH/MCH Device #0. This code is 80h indicating a peripheral device.
Bit 7:0
Description Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which GMCH/MCH falls. The code is 80h indicating other peripheral device.
3.9.7
BCC - Base Class Code Register (Device #0)
Address Offset: Default Value: Access: Size: 0Bh 08h Read Only 8 bits
This register contains the Base Class Code of the GMCH/MCH Device #0 Function #3. This code is 08h indicating a peripheral device.
Bit 7:0
Description Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class code for the GMCH/MCH. This code has the value 08h, indicating other peripheral device.
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Register Description
R
3.9.8
HDR - Header Type Register (Device #0)
Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. If Functions other than #0 are disabled this field returns a 00 to indicate that the GMCH/MCH is a single function device with standard header layout. The default is 80 Reads and Writes to this location have no effect.
3.9.9
SVID - Subsystem Vendor Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0
Description Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of the system board. After it has been Written once, it becomes Read Only.
3.9.10
ID - Subsystem Identification Register (Device #0)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h Read/Write Once 16 bits
This value is used to identify a particular subsystem.
Bit 15:0
Description Subsystem ID (SUBID): This field should be programmed during BIOS initialization. After it has been Written once, it becomes Read Only.
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Register Description
R
3.9.11
CAPPTR - Capabilities Pointer Register (Device #0)
Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list.
Bit 7:0
Description Pointer to the offset of the first capability ID register block: In this case there are no capabilities therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
3.9.12
STRAP - Strap Status (Device #0)
Address Offset: Default Value: Access: Size: A8-ABh Read Only 32 bits
Bit 31:27 26 25 24 23:0 Reserved
Description
Clock Config: Bit_2 Clock Config: Bit_1 Clock Config: Bit_0
Reserved
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Register Description
R
3.9.13
HPLLCC - HPLL Clock Control Register (Device #0)
Address Offset: Default Value: Access: Size: C0-C1h 00h Read Only 16 bits
Bit 15:11 10 Reserved
Description
HPLL VCO Change Sequence Initiate Bit: Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.
9
Hphase Reset Bit: 1 = Assert 0 = Deassert (default)
8:2 1:0
Reserved HPLL Clock Control: See the following tables below
Table 34. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Configurations
GFX Core Clock - Low (Render Core Frequency only) Intel 852GME GMCH Only 000 001 010 011 100 101 110 111 400 MHz 400 MHz 400 MHz 400 MHz 533 MHz 533 MHz 533 MHz 400 MHz 266 MHz 200 MHz 200 MHz 266 MHz 266 MHz 266 MHz 333 MHz 333 MHz 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz
(R)
Straps Read Through HPLLCC[2:0]: D0:F3:Register Offset C0-C1h, bits[2:0]
FSB Frequency
System Memory Frequency
GFX Core Clock - High (Render Core Frequency & Display Core Frequency) Intel 852GME GMCH Only 200 MHz 200 MHz 133 MHz 266 MHz 200 MHz 266 MHz 266 MHz 250 MHz
(R)
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Register Description
R
3.10
PCI to AGP Configuration Registers (Device #1, Function #0)
Register Symbol VID DID PCICMD1 PCISTS1 RID Register Start 00 02 04 06 08 Register End 01 03 05 07 08
Table 35. Device 1 is the Virtual PCI to AGP Bridge (Device #1, Function #0))
Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Sub-Class Code Base Class Code Header Type Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address Register I/O Limit Address Register Secondary Status Register Memory Base Address Register Memory Limit Address Register Prefetchable Memory Base Limit Address Reg. Prefetchable Memory Limit Address Reg. Default Value 8086h 3581h 0000h 00A0h 01h 02h SUBC1 BCC1 HDR1 PBUSN1 SBUSN1 SUBUSN1 SMLT1 0A 0B 0E 18 19 1A 1B 0A 0B 0E 18 19 1A 1B 04h 06h 01h 00h 00h 00h 00h RO RO RO RO R/W R/W RO,R/W RO RO RO, R/W RO, R/WC RO Access
IOBASE1 IOLIMIT1 SSTS1 MBASE1 MLIMIT1 PMBASE1
1C 1D 1E 20 22 24
1C 1D 1F 21 23 25
F0h 00h 02A0h FFF0h 0000h FFF0h
RO,R/W RO,R/W RO,R/WC RO,R/W RO,R/W RO,R/W
PMLIMIT1
26
27
0000h
RO,R/W
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Register Description
R
Register Name Bridge Control Register Error Command Register
Register Symbol BCTRL1 ERRCMD1
Register Start 3E 40
Register End 3E 40
Default Value 00h 00h
Access RO,R/W RO,R/W
3.10.1
VID1 - Vendor Identification (Device #1)
Address Offset: Default Value: Access: Size: 00h 8086h Read Only 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description
Vendor Identification Number: This is a 16-bit value assigned to Intel.
3.10.2
DID1 - Device Identification (Device #1)
Address Offset: Default Value: Access: Size: 02h 3581h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number: This is a 16-bit value assigned to the GMCH/MCH (3581h).
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Register Description
R
3.10.3
PCICMD1 - PCI Command Register (Device #1)
Address Offset: Default Value: Access: Size: 04h 0000h Read Only, Read/Write 16 bits
Bit 15:9 8 Reserved
Description
SERR Message Enable (SERRE): This bit is a global enable bit for Device #1 SERR messaging. The GMCH/MCH communicates the SERR# condition by sending an SERR message to the ICH4-M. If this bit is set to a 1, the GMCH/MCH is enabled to generate SERR messages over hub interface for specific Device 1 error conditions that are individually enabled in the BCTRL1 register. The error status is reported in the PCISTS1 register. If SERRE1 is reset to 0, then the SERR message is not generated by the GMCH/MCH for Device #1. Address/Data Stepping (ADSTEP): Address/data stepping is not implemented in the GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect. Reserved Memory Write and Invalidate Enable (MWIE): This bit is implemented as Read Only and returns a value of 0 when read. Special Cycle Enable (SCE): This bit is implemented as Read Only and returns a value of 0 when read. Bus Master Enable (BME): When the Bus Master Enabled is set to "0" (default), AGP Master initiated Frame# cycles will be ignored by the GMCH/MCH. The result is a master abort. Ignoring incoming cycles on the secondary side of the PCI to PCI bridge effectively disabled the bus master on the primary side. When 1, AGP master initiated Frame# cycles will be accepted by the GMCH/MCH if they hit a valid address decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.
7 6:5 4 3 2
1
Memory Access Enable (MAE): This bit must be set to 1 to enable the Memory and Pre-fetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. When set to 0 all of Device #1's memory space is disabled. IO Access Enable (IOAE): This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. When set to 0 all of Device #1's I/O space is disabled.
0
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Register Description
R
3.10.4
PCISTS1 - PCI Status Register (Device #1)
Address Offset: Default Value: Access: Size: 06h 00A0h Read Only, Read/Write Clear 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the "virtual" PCI to PCI bridge embedded within the GMCH/MCH.
Bit 15 14 Reserved
Description
Signaled System Error (SSE): This bit is set to 1 when GMCH/MCH Device#1 generates an SERR message over hub interface for any enabled Device #1 error condition. Device #1 error conditions are enabled in the ERRCMD, PCICMD1 and BCTRL registers. Device #1 error flags are read/reset from the ERRSTS and SSTS1 register. Software clears this bit by writing a 1 to it. Reserved Fast Back-to-Back (FB2B): Indicates that the AGP/PCI_B interface always supports fast back to back writes (set to 1). Reserved 66/60 MHz capability (CAP66): Since the AGP/PCI bus is 66 MHz capable (set to 1). Reserved
13:8 7 6 5 4:0
3.10.5
RID - Revision Identification (Device #1)
Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits
This register contains the revision number of the GMCH device #1. These bits are read only and writes to this register have no effect.
Bit 7:0
Description Revision Identification Number: This is an 8-bit value that indicates the revision identification number for the GMCH/MCH. Intel 852GME = 02 Intel 852PM = 02
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Register Description
R
3.10.6
SUBC1 - Sub-Class Code (Device #1)
Address Offset: Default Value: Access: Size: 0Ah 04h Read Only 8 bits
This register contains the Sub-Class Code for the GMCH/MCH Device #1. This code is 04h indicating a PCI-to-PCI bridge device.
Bit 7:0
Description Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the Device #1 of the GMCH/MCH falls. The code is 04h indicating a PCI to PCI bridge.
3.10.7
BCC1 - Base Class Code (Device #1)
Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits
This register contains the Base Class Code of the GMCH/MCH Device #1. This code is 06h indicating a Bridge device.
Bit 7:0
Description Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH device #1. This code has the value 06h, indicating a Bridge device.
3.10.8
HDR1 - Header Type (Device #1)
Address Offset: Default Value: Access: Size: 0Eh 01h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Description Header Type Register (HDR): This read only field always returns 01 to indicate that GMCH/MCH Device #1 is a single function device with bridge header layout. Writes to this location have no effect.
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Register Description
R
3.10.9
PBUSN1 - Primary Bus Number (Device #1)
Address Offset: Default Value: Access: Size: 18h 00h Read Only 8 bits
This register identifies that "virtual" PCI to PCI bridge is connected to bus #0.
Bit 7:0
Description Primary Bus Number (BUSN): Configuration software typically programs this field with the number of the bus on the primary side of the bridge. Since Device #1 is an internal device and its primary bus is always 0.
3.10.10
SBUSN1 - Secondary Bus Number (Device #1)
Address Offset: Default Value: Access: Size: 19h 00h Read/Write 8 bits
This register identifies the bus number assigned to the second bus side of the "virtual" PCI to PCI bridge i.e. to PCI_B/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP.
Bit 7:0
Description Secondary Bus Number (BUSN): This field is programmed by configuration software with the bus number assigned to PCI_B.
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Register Description
R
3.10.11
SUBUSN1 - Subordinate Bus Number (Device #1)
Address Offset: Default Value: Access: Size: 1Ah 00h Read/Write 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP.
Bit 7:0
Description Subordinate Bus Number (BUSN): This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the Device #1 bridge. When only a single PCI device resides on the AGP/PCI_B segment, this register will contain the same value as the SBUSN1 register.
3.10.12
SMLT1 - Secondary Bus Master Latency Timer (Device #1)
Address Offset: Default Value: Access: Size: 1Bh 00h Read Only, Read/Write 8 bits
This register controls the bus tenure of the GMCH/MCH on AGP/PCI the same way Device#0 MLT controls the access to the PCI_A bus.
Bit
Description
7:3 2:0
Secondary MLT Counter Value (MLT): Programmable, default = 0 (SMLT disabled) Reserved
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Register Description
R
3.10.13
IOBASE1 - I/O Base Address Register (Device #1)
Address Offset: Default Value: Access: Size: 1Ch F0h Read Only, Read/Write 8 bits
This register controls the CPU to PCI_B/AGP I/O access routing based on the following formula: IO_BASE=< address =Bit 7:4 3:0
Description I/O Address Base (IOBASE): Corresponds to A[15:12] of the I/O addresses passed by bridge 1 to AGP/PCI_B. Reserved
3.10.14
IOLIMIT1 - I/O Limit Address Register (Device #1)
Address Offset: Default Value: Access: Size: 1Dh 00h Read Only, Read/Write 8 bits
This register controls the CPU to PCI_B/AGP I/O access routing based on the following formula: IO_BASE=< address =Bit 7:4 3:0
Description I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address limit of Device #1. Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B. Reserved
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Register Description
R
3.10.15
SSTS1 - Secondary Status Register (Device #1)
Address Offset: Default Value: Access: Size: 1Eh 02A0h Read Only, Read/Write Clear 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with a secondary side (i.e. PCI_B/AGP side) of the "virtual" PCI to PCI bridge embedded within GMCH/MCH.
Bit 15
Description Detected Parity Error (DPE): This bit is set to a 1 to indicate GMCH/MCH's detection of a parity error in the address or data phase of PCI_B/AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to this bit. Reserved Received Master Abort Status (RMAS): When the GMCH/MCH terminates a Host to PCI_B/AGP with an unexpected master abort, this bit is set to 1. Software resets this bit to 0 by writing a 1 to it. Received Target Abort Status (RTAS): When a GMCH/MCH -initiated transaction on PCI_B/AGP is terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1 to 0 by writing a 1 to it. Reserved DEVSEL# Timing (DEVT): This 2-bit field indicates the timing of the DEVSEL# signal when the GMCH/MCH responds as a target on PCI_B/AGP, and is hard-wired to the value 01b (medium) to indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle. Reserved Fast Back-to-Back (FB2B): This bit is hardwired to 1, since GMCH/MCH as a target supports fast back-to-back transactions on PCI_B/AGP. Reserved 66/60 MHz capability (CAP66): The AGP/PCI_B bus is capable of 66Mhz operation (Set to 1) Reserved
14 13
12
11 10:9
8 7 6 5 4:0
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3.10.16
MBASE1 - Memory Base Address Register (Device #1)
Address Offset: Default Value: Access: Size: 20h FFF0h Read Only, Read/Write 16 bits
This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =Bit 15:4 3:0
Description Memory Address Base (MBASE): Corresponds to A[31:20] of the lower limit of the memory range that will be passed by the Device #1 bridge to AGP/PCI_B. Reserved
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Register Description
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3.10.17
MLIMIT1 - Memory Limit Address Register (Device #1)
Address Offset: Default Value: Access: Size: 22h 0000h Read Only, Read/Write 16 bits
This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =Bit 15:4
Description Memory Address Limit (MLIMIT): Corresponds to A[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the device 1 bridge to AGP/PCI_B. Reserved
3:0
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Register Description
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3.10.18
PMBASE1 - Prefetchable Memory Base Address Reg (Device #1)
Address Offset: Default Value: Access: Size: 24h FFF0h Read Only, Read/Write 16 bits
This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =Bit 15:4 3:0
Description Prefetchable Memory Address Base (PMBASE): Corresponds to A[31:20] of the lower limit of the address range passed by bridge device 1 across AGP/PCI_B. Reserved
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Register Description
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3.10.19
PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1)
Address Offset: Default Value: Access: Size: 26h 0000h Read Only, Read/Write 16 bits
This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =Bit 15:4 3:0
Description Prefetchable Memory Address Limit (PMLIMIT): Corresponds to A[31:20] of the upper limit of the address range passed by bridge Device #1 across AGP/PCI_B. Reserved
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Register Description
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3.10.20
BCTRL - Bridge Control Register (Device #1)
Address Offset: Default Value: Access: Size: 3Eh 00h Read Only, Read/Write 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI to PCI bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI_B/AGP) as well as some bits that affect the overall behavior of the "virtual" PCI to PCI bridge embedded within GMCH/MCH, e.g. VGA compatible address ranges mapping.
Bit 7:6 5 Reserved
Description
Master Abort Mode (MAMODE): This means when acting as a master on AGP/PCI_B the GMCH/MCH will drop writes on the floor and return all 1s during reads when a Master Abort occurs (Set to 1). Reserved VGA Enable (VGAEN): This bit controls the routing of CPU initiated transactions targeting VGA compatible I/O and memory address ranges. When this bit is set, the GMCH will forward the following CPU accesses to the AGP: 1) memory accesses in the range 0A0000h to 0BFFFFh 2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases - A[15:10] are not decoded) When this bit is set, forwarding of these accesses issued by the CPU is independent of the I/O address and memory address ranges defined by the previously defined base and limit registers. Forwarding of these accesses is also independent of the settings of the bit 2 (ISA Enable) of this register if this bit is "1". If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to hub interface. If the VGA enable bit is not set, then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses, i.e. the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to hub interface. If this bit is "0" (default), then VGA compatible memory and I/O range accesses are not forwarded to AGP. but rather they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT) The following table shows the behavior for all combinations of MDA and VGA: VGA MDA Behavior 0 0 1 1 0 1 0 1 All References to MDA and VGA Go To hub interface (Default) Reserved All References To VGA Go to AGP. MDA-only references (I/O Address 3BF and aliases) will go to hub interface. VGA References go to AGP; MDA references go to hub interface
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Bit 2
Description ISA Enable (ISAEN): Modifies the response by the GMCH/MCH to an I/O access issued by the CPU that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. When this bit is set to 1, GMCH/MCH will not forward to PCI_B/AGP any I/O transactions addressing the last 768 bytes in each 1-KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to PCI_B/AGP these cycles will be forwarded to hub interface where they can be subtractively or positively claimed by the ISA bridge. If this bit is 0 (default) then all addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions will be mapped to PCI_B/AGP. Reserved Parity Error Response Enable (PEREN): Controls GMCH/MCH's response to data phase parity errors on PCI_B/AGP. G_PERR# is not implemented by the GMCH/MCH. However, when this bit is set to 1, address and data parity errors detected on PCI_B are reported via the HI SERR messaging mechanism, if further enabled by SERRE1. If this bit is reset to 0, then address and data parity errors on PCI_B/AGP are not reported via the GMCH/MCH hub interface SERR messaging mechanism. Other types of error conditions can still be signaled via SERR messaging independent of this bit's state.
1 0
The bit field definitions for VGAEN and MDAP are detailed in the following table.
VGAEN: MDAP 00 01 10 11
Description All References to MDA and VGA space are routed to hub interface. Illegal combination All VGA references are routed to this bus. Exclusive MDA references are routed to hub interface. All VGA references are routed to this bus. All MDA references are routed to hub interface.
3.10.21
ERRCMD1 - Error Command Register (Device #1)
Address Offset: Default Value: Access: Size: 40h 00h Read Only, Read/Write 8 bits
Bit 7:1 0 Reserved
Description
SERR on Receiving Target Abort (SERTA): When this bit is 1 the GMCH/MCH generates an SERR message over hub interface upon receiving a target abort on PCI_B. When this bit is set to 0, the GMCH/MCH does not assert an SERR message upon receipt of a target abort on PCI_B. SERR messaging for Device #1 is globally enabled in the PCICMD1 register.
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Register Description
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3.11
Intel(R) 852GME GMCH Integrated Graphics Device Registers (Device #2, Function #0)
This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1.
Table 36. Integrated Graphics Device Configuration Space (Device #2, Function#0)
Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Cache Line Size Master Latency Timer Header Type Graphics Memory Range Address Memory Mapped Range Address IO Range Subsystem Vendor ID Subsystem ID Video Bios ROM Base Address Interrupt Line Interrupt Pin Register Symbol VID DID PCICMD PCISTS RID Address Offset 00h 02h 04h 06h 08h Regist er End 01h 03h 05h 07h 08h Default Value 8086h 3582h 0000h 0090h 01h 02h CC CLS MLT HDR GMADR MMADR IOBAR SVID SID ROMADR INTRLINE INTRPIN 09h 0Ch 0Dh 0Eh 10h 14h 18h 2Ch 2Eh 30h 3Ch 3Dh 0Bh 0Ch 0Dh 0Eh 13h 17h 1Bh 2Dh 2Fh 33h 3Ch 3Dh 030000h 00h 00h 00h 00000008h 00000000h 00000001h 0000h 0000h 00000000h 00h 01h RO RO RO RO RO,R/W RO,R/W RO,R/W R/WO R/ WO RO RO in F #1,R/W RO, Reserved In F#1 RO RO U1F1 C0F0 C0F0 C0F0 U1F1 U1F1 C0F0 C0F0 C0F0 Access RO RO RO,R/W RO RO Regs in Function#1 C0F0 C0F0 U1F1 U1F1 C0F0
Minimum Grant Maximum Latency
MINGNT MAXLAT
3Eh 3Fh
3Eh 3Fh
00h 00h
C0F0 C0F0
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Register Description
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Register Name Power Management Capabilities Power Management Control SWSMI Register Thermal INTR Command Register GMCH Clock Control Register
Register Symbol PMCAP
Address Offset D2h
Regist er End D3h
Default Value 0221h
Access RO
Regs in Function#1 C0F0
PMCS
D4h
D5h
0000h
RO,R/W
U1F1
SWSMI TINTRCMD GCCC
E0h Efh F0h
E1h EFh F1h
0000h 00h 0000h
R/W R/W R/W
3.11.1
VID - Vendor Identification Register (Device #2)
Address Offset: Default Value: Access Attributes: Size: 00-01h 8086h Read Only 16 bits
The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification Number: This is a 16-bit value assigned to Intel.
3.11.2
DID - Device Identification Register (Device #2)
Address Offset: Default Value: Access Attributes: Size: 02-03h 3582h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number: This is a 16-bit value assigned to the GMCH IGD (3582h).
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3.11.3
PCICMD - PCI Command Register (Device #2)
Address Offset: Default: Access: Size: 04-05h 0000h Read Only, Read/Write 16 bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to Main System memory.
Bit 15:10 9 8 7 6 5 4 3 2 Reserved Fast Back-to-Back (FB2B)RO. SERR# Enable (SERRE) RO Address/Data SteppingRO Parity Error Enable (PERRE) RO
Description
Video Palette Snooping (VPS) RO Memory Write and Invalidate Enable (MWIE) RO Special Cycle Enable (SCE) RO Bus Master Enable (BME) R/W: This bit determines if the IGD is to function as a PCI compliant master. 0= Disable IGD bus mastering (default). 1 = Enable IGD bus mastering.
1
Memory Access Enable (MAE) R/W: This bit controls the IGD's response to system memory space accesses. 0= Disable (default). 1 = Enable.
0
I/O Access Enable (IOAE) R/W: This bit controls the IGD's response to I/O Space accesses. 0 = Disable (default). 1 = Enable.
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Register Description
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3.11.4
PCISTS - PCI Status Register (Device #2)
Address Offset: Default Value: Access: Size: 06-07h 0090h Read Only 16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit 15 14 13 12 11 10:9 8 7 6 5 4
Description Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0. Signaled System Error (SSE) - RO Received Master Abort Status (RMAS) - RO Received Target Abort Status (RTAS) - RO Signaled Target Abort Status (STAS) - RO DEVSEL# Timing (DEVT) - RO Data Parity Detected (DPD) - RO Fast Back-to-Back (FB2B) - RO User Defined Format (UDF) - RO 66 MHz PCI Capable (66C) - RO CAP LIST: This bit is set to 1 to indicate that the register at 34h provides an offset into the Function's PCI Configuration Space containing a pointer to the location of the first item in the list. Reserved
3:0
3.11.5
RID - Revision Identification Register (Device #2)
Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits
This register contains the revision number of the IGD. These bits are Read Only and Writes to this register have no effect.
Bit 7:0
Description Revision Identification Number: This is an 8-bit value that indicates the revision identification number for the GMCH. Intel 852GME = 02 Intel 852PM = 02
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Register Description
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3.11.6
CC - Class Code Register (Device #2)
Address Offset: Default Value: Access: Size: 09-0Bh 030000h Read Only 24 bits
This register contains the device programming interface information related to the Sub-Class code and Base Class code definition for the IGD. This register also contains the Base Class code and the function sub-class in relation to the Base Class code.
Bit 23:16 15:8
Description Base Class Code (BASEC): 03=Display controller Sub-Class Code (SCC): Function 0: 00h=VGA compatible or 80h=Non VGA Function 1: 80h=Non VGA
7:0
Programming Interface (PI): 00h=Hardwired as a Display controller.
3.11.7
CLS - Cache Line Size Register (Device #2)
Address Offset: Default Value: Access: Size: 0Ch 00h Read only 8 bits
The IGD does not support this register as a PCI slave.
Bit 7:0 Cache Line Size (CLS) - RO
Description
3.11.8
MLT - Master Latency Timer Register (Device #2)
Address Offset: Default Value: Access: Size: 0Dh 00h Read Only 8 bits
The IGD does not support the programmability of the master latency timer because it does not perform bursts.
Bit 7:0
Description Master Latency Timer Count Value - RO
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3.11.9
HDR - Header Type Register (Device #2)
Address Offset: Default Value: Access: Size: 0Eh 00h Read Only 8 bits
This register contains the Header Type of the IGD.
Bit 7 6:0
Description Multi Function Status (MFunc): Indicates if the device is a multi-function device. Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has the value 00h, indicating a type 0 configuration space format.
3.11.10
GMADR - Graphics Memory Range Address Register (Device #2)
Address Offset: Default Value: Access: Size: 10-13h 00000008h Read/Write, Read Only 32 bits
IGD graphics system memory base address is specified in this register.
Bit 31:27 26 25:4 3 2:1 0
Description Memory Base AddressR/W: Set by the OS, these bits correspond to address signals [31:26]. 128-MB Address Mask - RO: 0 indicates 128-MB address Address MaskRO: Indicates (at least) a 32-MB address range. Prefetchable MemoryRO: Enable prefetching. Memory TypeRO: Indicate 32-bit address. Memory/IO SpaceRO: Indicate system memory space.
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3.11.11
MMADR - Memory Mapped Range Address Register (Device #2)
Address Offset: Default Value: Access: Size: 14-17h 00000000h Read/Write, Read Only 32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19].
Bit 31:19 18:4 3 2:1 0
Description Memory Base AddressR/W: Set by the OS, these bits correspond to address signals [31:19]. Address MaskRO: Indicate 512-kB address range. Prefetchable MemoryRO: Prevents prefetching. Memory TypeRO: Indicates 32-bit address. Memory / IO SpaceRO: Indicates system memory space.
3.11.12
IOBAR - I/O Base Address Register (Device #2)
Address offset: Default: Access: Size: 18-1Bh 00000001h Read/Write 16-bits
This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are programmable allowing the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8-bytes of I/O space are decoded. Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if internal graphics is disabled. Note that access to this IO BAR is independent of VGA functionality within Device #2. If accesses to this I/O bar are allowed, then the GMCH claims all 8-bit, 16-bit, or 32-bit I/O cycles from the CPU that falls within the 8B claimed.
Bit 31:16 15:3 2:1 0 Reserved
Description
IO Base AddressR/W: Set by the OS, these bits correspond to address signals [15:3]. Memory TypeRO: Indicates 32-bit address. Memory / IO SpaceRO
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3.11.13
SVID - Subsystem Vendor Identification Register (Device #2)
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits
Bit 15:0
Description Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a reset.
3.11.14
SID - Subsystem Identification Register (Device #2)
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h Read/Write Once 16 bits
Bit 15:0
Description Subsystem Identification: This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a reset.
3.11.15
ROMADR - Video BIOS ROM Base Address Registers (Device #2)
Address Offset: Default Value: Access: Size: 30-33h 00000000h Read Only 32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0's.
Bit 31:18 17:11 10:1 0 ROM Base AddressRO
Description
Address MaskRO: Indicates 256-kB address range. Reserved ROM BIOS EnableRO: Indicates ROM not accessible.
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3.11.16
INTRLINEInterrupt Line Register (Device #2)
Address Offset: Default Value: Access: Size: 3Ch 00h Read/Write 8 bits
Bit 7:0
Description Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the System Interrupt controller that the device's interrupt pin is connected to.
3.11.17
INTRPINInterrupt Pin Register (Device #2)
Address Offset: Default Value: Access: Size: 3Dh 01h Read Only 8 bits
Bit 7:0
Description Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. For Function #1, this register is set to 00h.
3.11.18
MINGNT - Minimum Grant Register (Device #2)
Address Offset: Default Value: Access: Size: 3Eh 00h Read Only 8 bits
Bit 7:0
Description Minimum Grant Value: The IGD does not burst as a PCI compliant master.
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Register Description
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3.11.19
MAXLAT - Maximum Latency Register (Device #2)
Address Offset: Default Value: Access: Size: 3Fh 00h Read Only 8 bits
Bit 7:0
Description Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to access the PCI bus.
3.11.20
PMCAP - Power Management Capabilities Register (Device #2)
Address Offset: Default Value: Access: Size: D2h-D3h 0221h Read Only 16 bits
Bit 15:11 10:6 5 4 3 2:0
Description PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired to 0 to indicate that the IGD does not assert the PME# signal. Reserved Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Auxiliary Power Source: Hardwired to 0. PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation. Version: Hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
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3.11.21
PMCS - Power Management Control/Status Register (Device #2)
Address Offset: Default Value: Access: Size: D4h-D5h 0000h Read/Write, Read Only 16 bits
Bit 15 14:9 8 7:2 1:0
Description PME_Status RO: This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold). Reserved PME_EnRO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled. Reserved PowerStateR/W: This field indicates the current power state of the IGD and can be used to set the IGD into a new power state. If software attempts to Write an unsupported state to this field, Write operation must complete normally on the bus, but the data is discarded and no state change occurs. On a transition from D3 to D0 the graphics controller is optionally Reset to initial values. Bits[1:0] 00 01 10 11 Power State D0 D1 D2 D3 Not Supported Default
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Register Description
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3.11.22
GCCC GMCH Clock Control Register
Address Offset: Default Value: Access: Size: F0-F1h 00 00h Read/Write 16 bits
Bit 15:10 9 Reserved
Description
Core Display Clock Gate Control (CD-Gate): 0 = Core Display Clock Trunk not Gated, Clock running to the Core. 1 = Core Display Clock Trunk Gated, Clock not running to the Core.
8
Core Render Clock Gate Control (CR-Gate): 0 = Core Render Clock Trunk not Gated, clock running to the core. 1 = Core Render Clock Trunk Gated, clock not running to the core.
7 6
Reserved Core Display Clock Control (CDCC): 0 = Core Display Clock = Core High Clock (CH). 1 = Core Display Clock = Core Low Clock (CL). NOTE: This bit can be set to a 1 only when CRCC is set to 01. Setting this to a 1'with any other combination of CRCC can cause irrecoverable failures. Gate both core Render and Display Clocks using CR Gate and CD Gate Registers, then change the value of CDCC Register and update CR Gate and CD Gate to re-enable the Clocks.
5:4
Core Render Clock Control (CRCC): 00 = Core Render Clock = Core High Clock (CH). 01 = Core Render Clock = Core Low Clock (CL). 10 = Reserved 11 = Reserved NOTE: CRCC defaults to 00 (CH) and only certain transitions are allowed. 00 01 01 00
Gate Core Render Clock using CR Gate Register, then change the value of CRCC Register and update CR Gate to re-enable the Clock. 3:0 Reserved
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System Address Map
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4
System Address Map
A system based on the GMCH/MCH supports 4 GB of addressable system memory space and 64 kB+3 B of addressable I/O space. The I/O and system memory spaces are divided by system configuration software into regions. The system memory ranges are useful either as system memory or as specialized system memory, while the I/O regions are used solely to control the operation of devices in the system. When the GMCH/MCH receives a Write request whose address targets an invalid space, the data is ignored. For Reads, the GMCH/MCH responds by returning all zeros on the requesting interface. There is a programmable memory address space under the 1-MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section. This section focuses on how the memory space is partitioned and how the separate memory regions are used. I/O address space has simpler mapping and is explained at the end of this section. The GMCH/MCH claims any CPU access over 4 GB and terminates the transaction without forwarding it to hub interface or AGP (Intel 852GME GMCH and Intel 852PM MCH only). Simply dropping the data terminates writes and for reads the GMCH/MCH return all zeros on the host bus. In the following sections, it is assumed that all of the compatibility memory ranges reside on the hub interface/PCI. The exception to this rule is VGA ranges, which may be mapped to AGP or to the internal graphics device (IGD). In the absence of more specific references, cycle descriptions referencing PCI should be interpreted as the hub interface/PCI, while cycle descriptions referencing AGP or IGD are related to the AGP bus or the internal graphics device respectively. The GMCH/MCH Memory Map includes a number of programmable ranges. All of these ranges must be unique and non-overlapping. There are no Hardware Interlocks to prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results.
4.1
System Memory Address Ranges
The Intel 852GME GMCH and Intel 852PM MCH provide a maximum system memory of 2 GB. The GMCH/MCH does not re-map APIC memory space and does not limit DDR SDRAM space in hardware. It is the BIOS or system designer's responsibility to limit system memory population so that adequate PCI, AGP, High BIOS and APIC memory space can be allocated. The figures below depict the system memory address map in a simplified form and provide details on mapping specific system memory regions as defined and supported by the GMCH/MCH.
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System Address Map
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Figure 7. Simplified View of Intel(R) 852GME GMCH and Intel(R) 852PM MCH System Address Map
4GB
PCI M emory Address Range
Graphic
(Local)
M emory
AGP Address Range
Graphics (AGP) Aperture
Top of the M ain M emory
M ain M emory Address Range
Independently Programmable Non-Overlapping M emory W indows
0
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System Address Map
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Figure 8. Detailed View of the Intel(R) 852GME GMCH and Intel(R) 852PM MCH System Address Map
4.2
MS-DOS* Compatibility Area
This compatibility region is divided into the following address regions: * Source synchronous 0 - 640 kB DOS Area * 640 - 768 kB Video Buffer Area * 768 - 896 kB in 16-kB sections (total of eight sections) - Expansion Area * 896 -960 kB in 16-kB sections (total of four sections) - Extended System BIOS Area * 960 kB - 1 MB System BIOS area There are 16 system memory segments in the compatibility area. Thirteen of the system memory ranges can be enabled or disabled independently for both Read and Write cycles.
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System Address Map
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Table 37. System Memory Segments and Their Attributes
System Memory Segments 000000H - 09FFFFH 0A0000H - 0BFFFFH Attributes Fixed - always mapped to main DDR SDRAM Mapped to hub interface, AGP or IGD - configurable as SMM space WE(Write Enable) RE (Read Enable) WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE Comments 0 to 640 kB - DOS Region Video Buffer (physical DDR SDRAM configurable as SMM space) Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension BIOS Area
0C0000H - 0C3FFFH 0C4000H - 0C7FFFH 0C8000H - 0CBFFFH 0CC000H - 0CFFFFH 0D0000H - 0D3FFFH 0D4000H - 0D7FFFH 0D8000H - 0DBFFFH 0DC000H - 0DFFFFH 0E0000H - 0E3FFFH 0E4000H - 0E7FFFH 0E8000H - 0EBFFFH 0EC000H - 0EFFFFH 0F0000H - 0FFFFFH
DOS Area (000000h-09FFFFh)
The DOS area is 640 kB in size and is always mapped to the main system memory controlled by the GMCH/MCH.
Legacy VGA Ranges (0A0000h-0BFFFFh)
The legacy 128-kB VGA memory range 0A0000h-0BFFFFh (VGA Frame Buffer) can be mapped to IGD (Device #2), to AGP/PCI1 (Device#1) and to the hub interface depending on the programming of the VGA steering bits. Priority for VGA mapping is constant in that the GMCH/MCH always decodes internally mapped devices first. Internal to the GMCH/MCH, decode precedence is always given to IGD. The GMCH/MCH always positively decodes internally mapped devices, namely the IGD and the AGP/PCI1. Subsequent decoding of regions mapped to the AGP/PCI1 or the hub interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP). This region is also the default for SMM space.
Compatible SMRAM Address Range (0A0000h-0BFFFFh)
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to physical DDR SDRAM at this address. Non-SMM-mode CPU accesses to this range are considered to be to the video buffer area as described above. AGP and hub interface originated cycles to enabled SMM space are not allowed and are considered to be to the video buffer area if
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IGD is not enabled. AGP cycles are allowed to master abort and hub interface writes are forwarded to AGP; hub interface reads are handled as invalid cycles. If IGD is enabled, all hub interface accesses are handled as invalid and AGP accesses are handled as invalid cycles.
Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD, AGP/PCI1 and the hub interface (depending on configuration bits). Since the monochrome adapter may be mapped to any one of these devices, the GMCH/MCH must decode cycles in the MDA range and forward them either to IGD, AGP/PCI1 or to hub interface. This capability is controlled by VGA steering bits and the legacy configuration bit (MDAP bit). In addition to the system memory range B0000h to B7FFFh, the GMCH/MCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah, and 3BFh and forwards them to the either the IGD, AGP/PCI1 or the hub interface.
Expansion Area (0C0000h-0DFFFFh)
This 128-kByte ISA Expansion region is divided into eight, 16-kB segments. Each segment can be assigned one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are mapped through GMCH/MCH and are subtractively decoded to ISA space. System memory that is disabled is not re-mapped.
Extended System BIOS Area (0E0000h-0EFFFFh)
This 64-kB area is divided into four, 16-kB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main DDR SDRAM or to hub interface. Typically, this area is used for RAM or ROM. System memory segments that are disabled are not re-mapped elsewhere.
System BIOS Area (0F0000h-0FFFFFh)
This area is a single 64-kB segment. This segment can be assigned Read and Write attributes. It is by default (after Reset) Read/Write disabled and cycles are forwarded to hub interface. By manipulating the Read/Write attributes, the GMCH/MCH can "shadow" BIOS into the main DDR SDRAM. When disabled, this segment is not re-mapped.
4.3
Extended System Memory Area
This system memory area covers 100000h (1-MB) to FFFFFFFFh (4 GB-1B) address range and it is divided into the following regions: * Main system memory from 1-MB to the top of system memory * AGP or PCI Memory space from the top of system memory to 4-GB with two specific ranges * APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh (4 GB-19 MB - 1) and FEE0_0000h (4 GB-18 MB) to FEEF_FFFFh (4 GB-17 MB-1B) * High BIOS area from 4-GB to 4-GB - 2-MB
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4.4
Main System Memory Address Range (0010_0000h to Top of Main Memory)
The address range from 1-MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH/MCH. The GMCH/MCH will forward all accesses to addresses within this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to hub interface. The GMCH/MCH provides a maximum DDR SDRAM address decode space of 4 -GB. The GMCH/MCH does not re-map APIC memory space. The GMCH/MCH does not limit DDR SDRAM address space in hardware.
4.4.1
15 MB - 16 MB Window
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in Device 0 space. Accesses within this hole are forwarded to the hub interface. The range of physical DDR SDRAM disabled by opening the hole is not re-mapped to the top of the memory - that physical DDR SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. Validation and customer SV teams also use it for some of their test cards and that is why it is being supported. There is no inherent BIOS request for the 15 MB-16 MB hole.
4.4.2
Pre-allocated System Memory
Voids of physical addresses that are not accessible as general system memory and reside within system memory address range (< TOM) are created for SMM-mode and legacy VGA graphics compatibility. It is the responsibility of the BIOS to properly initialize these regions. The number of UMA options has been extended. Allocation is at a fixed address in terms of rigid positioning of UMA system memory TOM-TSEG-UMA (size), but it is mapped at any available address by a PCI allocation algorithm. GMADR and MMADR are requested through BARs. The following table details the location and attributes of the regions. Enabling/Disabling these ranges are described in the Control Register Device #0: GCC.
Table 38. Pre-allocated System Memory
System Memory Segments 00000000H - 03E7FFFFH 03E80000H - 03F7FFFFH Attributes R/W R/W Comments Available system memory 62.5 -MB Pre-allocated Graphics VGA memory 1 MB (or 4/8/16/32- MB) when IGD is enabled 03F80000H - 03FFFFFFH 03F80000H - 03FFFFFFH SMM Mode Only - CPU Reads SMM Mode Only - CPU Reads TSEG Address Range TSEG Pre-allocated system memory
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4.4.2.1
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area.
4.4.2.2
HSEG
SMM mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. NonSMM mode processor accesses to enabled HSEG are considered invalid are terminated immediately on the FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are re-mapped to SMM space to maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are not allowed. Physical DDR SDRAM behind the HSEG transaction address is not re-mapped and is not accessible.
4.4.2.3
TSEG
TSEG is 1-MB in size and is at the top of physical system memory. SMM mode processor accesses to enabled TSEG access the physical DDR SDRAM at the same address. AGP and hub interface originated cycles to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes. When the extended SMRAM space is enabled, CPU accesses to the TSEG range without SMM attribute or without WB attribute are forwarded to the hub interface. Non-SMM mode CPU accesses to enabled TSEG are considered invalid and are terminated immediately on the FSB. The exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical SMM space to maintain cache coherency. Hub interface originated cycles that enable SMM space are not allowed. The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this range are forwarded to the hub interface. When SMM is enabled the amount of system memory available to the system is equal to the amount of physical DDR SDRAM minus the value in the TSEG register which is fixed at 1 MB for the Intel 852GME GMCH and Intel 852PM MCH.
4.4.2.4
Dynamic Video Memory Technology (DVMT)
The IGD supports DVMT in a non-graphics system memory configuration. DVMT is a mechanism that manages system memory and the internal graphics device for optimal graphics performance. DVMT-enabled software drivers, working with the memory arbiter and the operating system, utilize the system memory to support 2D graphics and 3D applications. DVMT dynamically responds to application requirements by allocating the proper amount of display and texturing memory.
4.4.2.5
PCI Memory Address Range (Top of Main System Memory to 4 GB)
The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory space supported by the GMCH/MCH) is normally mapped via the hub interface to PCI. With an internal graphics configuration (Intel 852GME GMCH), there are two exceptions to this rule.
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1. 2.
The first exception is addresses decoded to the Graphics Memory range. One per function in device #2. The second exception is addresses decoded to the system memory mapped range of the Internal Graphics device. One per function in device #2. Both exception cases are forwarded to the Internal Graphics device.
As an AGP configuration, there are two exceptions to this rule: 1. Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT, PMBASE, and PMLIMIT registers are mapped to AGP. 2. Addresses decoded to the Graphics Aperture Range defined by the APBASE and APSIZE registers are mapped to the main DDR SDRAM. There are two sub-ranges within the PCI Memory address range defined as APIC configuration space and High BIOS Address range. As an Internal Graphics device, the Graphics Memory range and the Memory mapped range of the Internal Graphics device MUST NOT overlap with these two ranges. Similarly, as an AGP device, the AGP memory window and Graphics Aperture Window MUST NOT overlap with these two ranges. These ranges are described in detail in the following paragraphs.
4.4.2.6
APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000hFEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh. Processor accesses to the Local APIC configuration space do not result in external bus activity since the Local APIC configuration space is internal to the CPU. However, an MTRR must be programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in each processor should be relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64-kB for the Local and I/O APICs. The I/O APIC(s) usually resides in the ICH4-M portion of the chip-set or as a stand-alone component(s). I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit number 0 through F (hex). This address range will be normally mapped to hub interface. The address range between the APIC configuration space and the High BIOS (FED0_0000h to FFDF_FFFFh) is always mapped to the hub interface.
4.4.2.7
High BIOS Area (FFE0_0000h -FFFF_FFFFh)
The top 2 MB of the Extended Memory region is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to hub interface so that the upper subset of this region aliases to 16-MB to 256-kB range. The actual address space required for the BIOS is less than 2-MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered.
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4.4.2.8
AGP Memory Address Ranges
The GMCH/MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in GMCH/MCH's Device #1 configuration space. The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers. Conceptually, address decoding for each range follows the same basic concept. The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of a memory address . For the purpose of address decoding, the GMCH/MCH assumes that address bits A[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address are FFFFFh. This forces each memory address range to be aligned to 1MB boundary and to have a size granularity of 1MB. The GMCH/MCH positively decodes memory accesses to AGP memory address space as defined by the following equations: Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address Memory_Base_Address Address Memory_Limit_Address The window size is programmed by the plug-and-play configuration software. The window size depends on the size of memory claimed by the AGP device. Normally these ranges will reside above the Top-of-Main-Memory and below High BIOS and APIC address ranges. They normally reside above the top of memory (TOM) so they do not steal any physical DDR SDRAM memory space. It is essential to support a separate Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. Note that the GMCH/MCH Device #1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP that require such a window. These devices would include the AGP device, PCI-66 MHz/3.3 V agents, and multifunctional AGP devices where one or more functions are implemented as PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows.
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4.4.3
System Management Mode (SMM) Memory Range
The GMCH/MCH supports the use of main system memory as System Management RAM (SMM RAM) enabling the use of System Management mode. The GMCH/MCH supports three SMM options: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a system memory area that is available for the SMI handler's and code and data storage. This system memory resource is normally hidden from the system OS so that the processor has immediate access to this system memory space upon entry to SMM. The GMCH/MCH provides three SMRAM options: * Below 1 MB option that supports compatible SMI handlers. * Above 1 MB option that allows new SMI handlers to execute with Write-back cacheable SMRAM. * Above 1-MB solutions require changes to compatible SMRAM handler's code to properly execute above 1 MB. The optional larger write-back cacheable TSEG area from 128 kB to 1 MB in size above 1 MB is reserved from the highest area in DDR SDRAM memory. The above 1 MB solutions require changes to compatible SMRAM handler's code to properly execute above 1 MB. Note: Hub interface and AGP masters are not allowed to access the SMM space. This must be ensured even for the GTLB translation.
4.4.3.1
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang: * The Compatible SMM space must not be set-up as cacheable. * High or TSEG SMM transaction address space must not overlap address space assigned to DDR SDRAM, the AGP aperture range, or to any PCI devices (including hub interface and graphics devices). This is a BIOS responsibility. * Both D_OPEN and D_CLOSE must not be set to 1 at the same time. * When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available. This is a BIOS responsibility. * Any address translated through the AGP Aperture GTLB must not target DDR SDRAM from 000A0000h to 000FFFFFh.
4.4.3.2
SMM Space Definition
SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The addressed SMM space is defined as the range of bus addresses used by the CPU to access SMM space. DDR SDRAM SMM space is defined as the range of physical DDR SDRAM locations containing the SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible, High, and TSEG. The Compatible and TSEG SMM space is not re-mapped and therefore the addressed and DDR SDRAM SMM space is the same address range. Since the High SMM space is re-mapped the addressed and DDR SDRAM SMM space is a different address
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range. Note that the High DDR SDRAM space is the same as the Compatible Transaction Address space. Table 46 describes three unique address ranges: 1. Compatible Transaction Address (Adr C) 2. High Transaction Address (Adr H) 3. TSEG Transaction Address (Adr T) These abbreviations are used later. Table 39. SMM Space Transaction Handling
SMM Space Enabled Compatible (C) High (H) TSEG (T) Transaction Address Space (Adr) A0000h to BFFFFh 0FEDA0000h to 0FEDBFFFFh (TOM-TSEG_SZ) to TOM DRAM Space (DRAM) A0000h to BFFFFh A0000h to BFFFFh (TOM-TSEG_SZ) to TOM
4.4.3.3
SMM Access through GART/GTT TLB
CPU accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space are not allowed. Writes will be routed to memory address 0h with byte enables deasserted and reads will be routed to memory address 0h. If a GART/GTT TLB translated address hits enabled SMM DDR SDRAM space, the Invalid Graphics Aperture Translation Table Entry Flag (ITTEF) in the ERRSTS register is set. AGP and hub interface originated accesses are never allowed to access SMM space directly or through the GART/GTT TLB address translation. If a GART/GTT TLB translated address hits enabled SMM SDRAM space, the Invalid Graphics Aperture Translation Table Entry Flag (ITTEF) in the ERRSTS register is set. AGP (PIPE/SBA) write accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be re-mapped to address 0h with de-asserted byte enables. AGP (PIPE/SBA) read accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be re-mapped to address 0h. AGP (FRAME) write accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be re-mapped to address 0h with de-asserted byte enables. AGP (PIPE/SBA) read accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be re-mapped to address 0h. All hub interface originated cycles are snooped and subsequently decoded on the FSB. Hub interface write accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be snooped and then remapped to address 0h with de-asserted byte enables. Hub interface read accesses through GART/GTT TLB address translation to enabled SMM DDR SDRAM space will be snooped and remapped to address 0h. Any WB resulting from the snoop will be written to enabled SMM DDR SDRAM. For CPU, AGP (SBA, PIPE and FRAME), and hub interface originated accesses, if a GART/GTT TLB translated address hits enabled High SMM transaction space, the access will go to DDR SDRAM (if 256-MB SDRAM or more) without being re-mapped.
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4.4.4
System Memory Shadowing
Any block of system memory that can be designated as Read-Only or Write-Only can be "shadowed" into GMCH/MCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR SDRAM is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed accordingly.
4.4.5
I/O Address Space
The GMCH/MCH does not support the existence of any other I/O devices beside itself on the CPU bus. The GMCH/MCH generates hub interface or PCI bus cycles for all CPU I/O accesses that it does not claim. Within the host bridge the GMCH/MCH contains two internal registers in the CPU I/O space, Configuration Address register (CONFIG_ADDRESS) and the Configuration Data register (CONFIG_DATA). These locations are used to implement Configuration Space Access Mechanism and as described in the Configuration register section. The processor allows 64-kB +3-B to be addressed within the I/O space. The GMCH/MCH propagates the CPU I/O address without any translation on to the destination bus and therefore provides addressability for 64-k+3-B locations. Note that the upper three locations can be accessed only during I/O address wrap-around when CPU bus A16# address signal is asserted. A16# is asserted on the CPU bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh. A set of I/O accesses (other than ones used for configuration space access) is consumed by the internal graphics device if it is enabled. The I/O accesses (other than ones used for configuration space access) are forwarded normally to the hub interface bus unless they fall within the AGP I/O address range as defined by the mechanisms explained below. The GMCH will not post I/O Write cycles to IDE. The PCICMD1 register can disable the routing of I/O cycles to the AGP. The GMCH/MCH never responds to I/O cycles initiated on AGP.
4.4.5.1
AGP/PCI I/O Address Mapping
The GMCH/MCH can be programmed to direct non-memory (I/O) accesses to the AGP bus interface when CPU initiated I/O cycle addresses are within the AGP I/O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH/MCH Device #1 configuration space. Address decoding for this range is based on the following concept. The top 4 bits of the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the purpose of address decoding, the GMCH/MCH assumes that lower 12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O address range alignment to 4-kB boundary and produces a size granularity of 4 kB.
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The GMCH/MCH positively decodes I/O accesses to AGP I/O address space as defined by the following equation: I/O_Base_Address CPU I/O Cycle Address I/O_Limit_Address The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the AGP device. The GMCH/MCH also forwards accesses to the Legacy VGA I/O ranges according to the settings in the Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a second adapter (monochrome) is present on the hub interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the GMCH/MCH will decode legacy monochrome IO ranges and forward them to the hub interface. The IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh. The GMCH/MCH Device #1 I/O address range registers defined above are used for all I/O space allocation for any devices requiring such a window on AGP. These devices would include the AGP device, PCI66 MHz/3.3 V agents, and multifunctional AGP devices where one or more functions are implemented as PCI devices. The PCICMD1 register can disable the routing of I/O cycles to the AGP.
4.4.6
GMCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three interfaces i.e. Host bus, IGD, and hub interface or AGP.
4.4.6.1
Hub Interface Decode Rules
The GMCH/MCH accepts accesses from hub interface to the following address ranges: * All memory read and write accesses to main DDR SDRAM including PAM region (except SMM space) * All memory read/write accesses to the Graphics Aperture (DDR SDRAM) defined by APBASE and APSIZE. * All hub interface memory write accesses to AGP memory range defined by MBASE, MLIMIT, PMBASE, and PMLIMIT. * Memory writes to VGA range on AGP if enabled. All memory reads from the hub interface A that are targeted > 4-GB memory range will be terminated with Master Abort completion, and all memory writes (>4-GB) from the hub interface will be ignored. Hub interface memory accesses that fall elsewhere within the memory range are considered invalid and will be re-mapped to memory address 0h, snooped on the host bus, and dispatched to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BEs deasserted and will terminate with Master Abort if completion is required. I/O cycles will not be accepted. They are terminated with Master Abort completion packets.
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4.4.6.1.1
Hub Interface Accesses to GMCH/MCH that Cross Device Boundaries
Hub interface accesses are limited to 256-bytes but have no restrictions on crossing address boundaries. A single hub interface request may therefore span device boundaries (AGP, DDR SDRAM) or cross from valid addresses to invalid addresses (or vise versa). The GMCH/MCH does not support transactions that cross device boundaries. For reads and for writes requiring completion, the GMCH/MCH will provide separate completion status for each naturally aligned 32 -or 64 -byte block. If the starting address of a transaction hits a valid address, the portion of a request that hits that target device (AGP or DDR SDRAM) will complete normally. The remaining portion of the access that crosses a device boundary (targets a different device than that of the starting address) or hits an invalid address will be remapped to memory address 0h, snooped on the host bus, and dispatched to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BEs deasserted and will terminate with Master Abort if completion is required. If the starting address of a transaction hits a invalid address the entire transaction will be remapped to memory address 0h, snooped on the host bus, and dispatched to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BEs deasserted and will terminate with Master Abort if completion is required.
4.4.6.1.2
AGP Interface Decode Rules Cycles Initiated Using PCI Protocol
The GMCH/MCH does not support any AGP/PCI access targeting hub interface. The GMCH will claim AGP/PCI initiated memory read and write transactions decoded to the main DDR SDRAM range or the Graphics Aperture range. All other memory read and write requests will be masteraborted by the AGP/PCI initiator as a consequence of GMCH/MCH not responding to a transaction. Under certain conditions, the GMCH/MCH restricts access to the DOS Compatibility ranges governed by the PAM registers by distinguishing access type and destination bus. The GMCH/MCH accepts AGP/PCI write transactions to the compatibility ranges if the PAM designates DDR SDRAM as write-able. If accesses to a range are not write-enabled by the PAM, the GMCH/MCH does not respond and the cycle will result in a master-abort. The GMCH/MCH accepts AGP/PCI read transactions to the compatibility ranges if the PAM designates DDR SDRAM as readable. If accesses to a range are not read enabled by the PAM, the GMCH/MCH do not respond and the cycle will result in a master-abort. If agent on AGP/PCI issues an I/O or PCI Special Cycle transaction, the GMCH will not respond and cycle will result in a master-abort. The GMCH will accept PCI configuration cycles to the internal GMCH devices as part of the PCI configuration/co-pilot mode mechanism.
Cycles Initiated Using AGP Protocol
All cycles must reference main memory i.e. main DDR SDRAM address range (excluding PAM) or Graphics Aperture range (also physically mapped within DDR SDRAM but using different address range). AGP accesses to the PAM region from 640 kB to 1 MB are not allowed. AGP accesses to SMM space are not allowed. AGP initiated cycles that target DDR SDRAM are not snooped on the host bus, even if they fall outside of the AGP aperture range.
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If a cycle is outside of a valid main memory range then it will terminate as follows: Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error flag. Writes: Re-mapped to memory address 0h with BE's de-asserted (effectively dropped "on the floor") and set the IAAF error flag.
AGP Accesses to GMCH/MCH that Cross Device Boundaries
For FRAME# accesses, when an AGP or PCI master gets disconnected it will resume at the new address which allows the cycle to be routed to or claimed by the new target. Therefore accesses should be disconnected by the target on potential device boundaries. The GMCH/MCH will disconnect AGP/PCI transactions on 4-kB boundaries. AGPPIPE# and SBA accesses are limited to 256 bytes and must hit DDR SDRAM. AGP accesses are dispatched to DDR SDRAM on naturally aligned 32 - byte block boundaries. The portion of the request that hits a valid address will complete normally. The portion of a read access that hits an invalid address will be re-mapped to address 0h, return data from address 0h, and set the IAAF error flag. The portion of a write access that hits an invalid address will be re-mapped to memory address 0h with BE's de-asserted (effectively dropped "on the floor") and set the IAAF error flag.
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5
5.1
Functional Description
Host Interface Overview
The processor system bus uses source synchronous transfers for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At 100 MHz bus frequency, the two address signals run at 200 MT/s for a maximum address queue rate of 50 M addresses/sec. The data is quad pumped and an entire 64 bits cache line can be transferred in two bus clocks. At 133 MHz bus frequency, the data signals run at 533-MT/s for a maximum bandwidth of 4.3-GB/s.
5.2
Dynamic Bus Inversion
The GMCH/MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from the Host bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the power consumption of the GMCH/MCH. DINV[3:0] indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
Table 40. Relation of DBI Bits to Data Bits
DINV[3:0] DINV[0]# DINV[1]# DINV[2]# DINV[3]# Data Bits HD[15:0]# HD[31:16]# HD[47:32]# HD[63:48]#
Whenever the processor or the GMCH/MCH drive data, each 16-bit segment is analyzed. If more than eight of the 16 data signals would normally be driven low on the bus the corresponding DINV# signal will be asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or the GMCH/MCH receive data, they monitor DINV[3:0]# to determine if the corresponding data segment should be inverted.
5.2.1
System Bus Interrupt Delivery
Each processor supports system bus interrupt delivery. They do not support the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the System Bus as "Interrupt Message Transactions." System bus interrupts may originate from the processor on the system bus, or from a downstream device on hub interface. The ICH4-M contains IOxAPICs and its interrupts are generated as upstream hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI's (Message Signaled Interrupts) that are also in the form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on its
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PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface Memory Write. Alternatively the MSI may be directed directly to the system bus. The target of an MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound hub interface Memory Writes to address 0FEEx_xxxxh, to the System Bus as "Interrupt Message Transactions".
5.2.2
Upstream Interrupt Messages
The GMCH/MCH accepts message based interrupts from its hub interface and forwards them to the System Bus as Interrupt Message Transactions. The interrupt messages presented to the GMCH/MCH are in the form of Memory Writes to address 0FEEx_xxxxh. At the hub interface, the Memory Write interrupt message is treated like any other Memory Write; it is either posted into the inbound data buffer (if space is available) or retried (if data buffer space is not immediately available). Once posted, the Memory Write from the hub interface, to address 0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by the GMCH/MCH to the System Bus as an Interrupt Message transaction.
5.3
5.3.1
System Memory Interface
DDR SDRAM Interface Overview
The Intel 852GME GMCH and Intel 852PM MCH support DDR SDRAM at 200/266/333 MHz, respectively. The GMCH/MCH includes support for: * Up to 2-GB of PC2100/2700 DDR SDRAM * PC2100/2700 unbuffered 200-pin DDR SO-DIMMs * Maximum of 2 SO-DIMMs, single-sided and/or double-sided/or stacked The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH/MCH to support 64-bit wide SO-DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology. While address lines SMA[9:0] determine the starting address for a burst, burst lengths can be 4 or 8. Four chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM SO-DIMMs and four rows of double-sided DDR SDRAM SO-DIMMs. The GMCH/MCH main memory controller targets CAS latencies of 2 and 2.5 for DDR SDRAM. The GMCH/MCH provides refresh functionality with a programmable rate (normal DDR SDRAM rate is 1 refresh/15.6 s). For write operations of less than a full cache line, the GMCH/MCH will perform a cache-line read and into the write buffer and perform byte-wise write-merging in the write buffer.
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5.3.2
5.3.2.1
Memory Organization and Configuration
Configuration Mechanism for SO-DIMMs
Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification. Before any cycles to the system memory interface can be supported, the GMCH/MCH DDR SDRAM registers must be initialized. The GMCH/MCH must be configured for operation with the installed system memory types. Detection of system memory type and size is done via the System Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR SDRAM type and size information from the Serial Presence Detect port on the DDR SDRAM SO-DIMMs. DDR SDRAM SO-DIMMs contain a 5-pin Serial Presence Detect interface, including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit address. For the DDR SDRAM SO-DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the system management bus on the ICH4-M. Thus data is read from the Serial Presence Detect port on the SO-DIMMs via a series of I/O cycles to the south bridge. The BIOS needs to determine the size and type of system memory used for each of the rows of system memory in order to properly configure the GMCH/MCH system memory interface. For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel(R) 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (252337-001) for more detail.
5.3.2.2
System Memory Register Programming
This section provides summary of how the required information for programming the DDR SDRAM registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis), DDR SDRAM timings, row sizes and row page sizes. The following table lists a subset of the data available through the on board Serial Presence Detect ROM on each SO-DIMM.
Table 41. Data Bytes on SO-DIMM Used for Programming DDR SDRAM Registers
Byte 2 3 4 5 11 12 17 System Memory Type (DDR SDRAM) Number of Row Addresses, not counting Bank Addresses Number of Column Addresses Number of SO-DIMM banks ECC, No ECC Refresh Rate/Type Number Banks on each Device Description
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The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively provide enough data for programming the GMCH/MCH DDR SDRAM registers.
5.3.3
DDR SDRAM Performance Description
The overall system memory performance is controlled by the DDR SDRAM timing register, pipelining depth used in GMCH/MCH, system memory speed grade and the type of DDR SDRAM used in the system. Besides this, the exact performance in a system is also dependent on the total system memory supported, external buffering and system memory array layout. The most important contribution to overall performance by the system memory controller is to minimize the latency required to initiate and complete requests to system memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total flight time to complete a cache line request. A true discussion of performance really involves the entire chipset, not just the system memory controller.
5.3.4
Intel(R) 852GME GMCH and Intel(R) 852PM MCH Data Integrity (ECC)
The GMCH/MCH supports single-bit Error Correcting Code (or Error Checking and Correcting) (ECC) and multiple-bit Error Checking (EC) on the main memory interface. The GMCH/MCH generates an 8-bit code word for each 64-bit Qword of memory. GMCH/MCH performs two Qword writes at a time so two 8-bit codes are sent with each write. Since the code word covers a full Qword, writes of less than a Qword require a read-merge-write operation. Consider a Dword write to memory. In this case, when in ECC mode, GMCH/MCH will read the Qword where the addressed Dword will be written, merge in the new Dword, generate a code covering the new Qword and finally write the entire Qword and code back to memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected before merging the new Dword. The GMCH/MCH also supports another data integrity mode, EC mode. In this mode, the GMCH/MCH generates and stores a code for each Qword of memory. It then checks the code for reads from memory but does not correct any errors that are found.
5.4
Integrated Graphics Overview
The GMCH provides a highly integrated graphics accelerator and PCI set while allowing a flexible integrated system graphics solution.
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Figure 9. Intel(R) 852GME GMCH Graphics Block Diagram
DDR/SDRAM
Memory Control
Overlay Sprite Cursor Cursor Primary Display Secondary Display Display C 2nd Overlay DDC Alpha Blend/ Gamma/ CRC
DAC
Video Engine (MPEG2 Decode) 2D Engine 3D Engine Instr./ Data Setup/Transform Scan Conversion Texture Engine Raster Engine
LVDS Cntl Mux Port
DVOB
AGP2.0
DVOC
A_gmch_blk
High bandwidth access to data is provided through the system memory port. The GMCH accesses UMA memory located in system memory at 1.06 GB/s. The GMCH uses a tiling architecture to minimize page miss latencies and thus maximize effective rendering bandwidth.
5.4.1
Intel(R) GMCH 3D/2D Instruction Processing
The GMCH contains an extensive set of instructions that control various functions including 3D rendering, BLT operations, display, MPEG decode acceleration, and overlay. The 3D instructions set 3D pipeline states and control the processing functions. The 2D instructions provide an efficient method for invoking BLT operations.
5.4.2
3D Engine
The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. The GMCH supports the following: * Perspective-correct texture mapping * Multitextures * Embossed and Dot-Product Bump mapping * Cubic Environment Maps * Bilinear, Trilinear, and Anisotropic MIP mapped filtering
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* Gouraud shading * Alpha-blending * Per Vertex and Per- Pixel fog * Z/W buffering These features are independently controlled via a set of 3D instructions. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the Setup Engine, Scan Converter, Texture Pipeline, and Raster Pipeline. A typical programming sequence would be to send instructions to set the state of the pipeline followed by rendering instructions containing 3D primitive vertex data.
5.4.2.1
Setup Engine
The GMCH 3D setup engine takes the input data associated with each vertex of a 3D primitive and computes the various parameters required for scan conversion. In formatting this data, the GMCH maintains sub-pixel accuracy. The per Vertex data is converted into gradients that can be used to interpolate the data at any pixel within a polygon (colors, alpha, Z or W depth, fog, and texture coordinates). The pixels covered by a polygon are identified and per-pixel texture addresses are calculated.
5.4.2.2
Viewport Transform and Perspective Divide
A 3D-geometry pipeline typically involves transformation of vertices from model space to clipping space followed by clip test and clipping. Lighting can be performed during the transformation or at any other point in the pipeline. After clipping, the next stage involves perspective divide followed by transformation to the viewport or screen space. The GMCH can support Viewport Transform and Perspective Divide portion of the 3D geometry pipeline in hardware.
5.4.2.3
3D Primitives and Data Formats Support
The 3D primitives rendered by the GMCH are points, lines, discrete triangles, line strips, triangle strips, triangle fans, and polygons. In addition to this, the GMCH supports DirectX* Flexible Vertex Format* (FVF), which enables the application to specify a variable length parameter list, obviating the need for sending unused information to the hardware. Strips, Fans, and Indexed Vertices as well as FVF improve the delivered vertex rate to the setup engine significantly.
5.4.2.4
Pixel Accurate Fast Scissoring and Clipping Operation
The GMCH supports clipping to a scissoring rectangle within the drawing window. The GMCH clipping and scissoring in hardware reduce the need for software to process polygons, and thus improves performance. During the setup stage, the GMCH clips polygons to the drawing window. The scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. The scissor rectangle is pixel accurate, and independent of line and point width. The GMCH supports a single scissor box rectangle.
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5.4.2.5
Backface Culling
As part of the setup, the GMCH can discard polygons from further processing, if they are either facing away from or towards the user's viewpoint. This operation, referred to as "Back Face Culling" is accomplished based on the "clockwise" or "counter-clockwise" orientation of the vertices on a primitive. This can be enabled or disabled by the driver.
5.4.2.6
Scan Converter
The Scan Converter takes the vertex and edge information is used to identify all pixels that are affected by features being rendered. It works on a per-polygon basis, and one polygon may be entering the pipeline while calculations finish on another.
5.4.2.7
Texture Engine
The GMCH allows an image pattern, or video to be placed on the surface of a 3D polygon. The texture engine performs texture color or chromakey matching texture filtering (an-isotropic, trilinear, and bilinear), and YUV to RGB conversion. As texture sizes increase beyond the bounds of graphics memory, executing textures from graphics memory becomes impractical. Every rendering pass would require copying each and every texture in a scene from system memory to graphics memory, then using the texture, and finally overwriting the local memory copy of the texture by copying the next texture into graphics memory. The GMCH, using the Intel Direct Memory Execution model, simplifies this process by rendering each scene using the texture located in system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data.
5.4.2.8
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, it is important that texture be mapped in perspective as well. Without perspective correction, texture is distorted when an object recedes into the distance. Perspective correction involves a compute-intensive "per-pixel-divide" operation on each pixel. Perspective correction is necessary for realistic 3D graphics.
5.4.2.9
Texture Decompression
As the textures' average size gets larger with higher color depth and multiple textures become the norm, it becomes increasingly important to provide support for compressed textures. DirectX* supports Texture Compression/Decompression to reduce the bandwidth required to deliver textures. The GMCH supports several compressed texture formats (DirectX: DXT1, DXT2, DXT3, DXT4, DXT5) and OpenGL* FXT1 formats.
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5.4.2.10
Texture Chromakey
Chromakey is a method for removing a specific color or range of colors from a texture map before it is applied to an object. For "nearest" texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). For "linear" texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range). Chromakeying can be performed for both paletted and non-paletted textures, and removes texels that fall within a specified color range. The Chromakey mode refers to testing the RGB or YUV components to see if they fall between high and low state variable values. If the color of a texel contribution is in this range and chromakey is enabled, then this contribution is removed from the resulting pixel color.
5.4.2.11
Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the moire patterns, which occur as a result of the fact that there is very small number of pixels available on screen to contain the data of a high-resolution texture map. Full Scene Anti-Aliasing uses super-sampling, which means that the image is rendered internally at a higher resolution than it is displayed on screen. The GMCH can render internally at 1600x1200 and then this image is down-sampled (via a Bilinear filter) to the screen resolution of 640x480 and 800x600. Full Scene Anti-aliasing removes jaggies at the edges as well as moire patterns. The GMCH renders the super-sampled image up to 2K x 2K pixel dimensions. The GMCH then reads it as a texture and bilinearly filters it to the final resolution.
5.4.2.12
Texture Map Filtering
Many texture-mapping modes are supported. Perspective correct mapping is always performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). The way a texture is combined with other object attributes is also definable. The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1 texels. (A texel is defined as a texture map element.) Included in the texture processor is a texture cache, which provides efficient MIP-mapping. The GMCH supports seven types of texture filtering: * Nearest (also known as Point Filtering): Texel with coordinates nearest to the desired pixel is used. (This is used if only one LOD is present.) * Linear (also known as Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the desired pixel is used. (This is used if only one LOD is present.) * Nearest MIP Nearest (also known as Point Filtering): This is used if many LODs are present. The nearest LOD is chosen and the texel with coordinates nearest to the desired pixel is used.
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* Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel is used (four texels). This is also referred to as Bilinear MIP Mapping. * Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two appropriate LODs are selected and within each LOD the texel with coordinates nearest to the desired pixel are selected. The Final texture value is generated by linear interpolation between the two texels selected from each of the MIP Maps. * Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture value is generated by linear interpolation between the two texels generated for each of the MIP Maps. Trilinear MIP Mapping is used to minimize the visibility of LOD transitions across the polygon. * Anisotropic MIP Nearest (Anisotropic Filtering): This filter can be used when textured object pixels map back to significantly non-square regions of the texture (e.g., when the texture is scaled in one screen direction than the other screen direction). * Both DirectX and OGL (Rev.1.1) allow support for all these filtering modes.
5.4.2.13
Multiple Texture Composition
The GMCH also performs multiple texture composition. This allows the combination of two or greater MIP maps to produce a new one with new LODs and texture attributes in a single or iterated pass. The setup engine supports up to four texture map coordinates in a single pass. The GMCH allows up to two Bilinear MIP Maps or a single Trilinear MIP Map to be composited in a single pass. Greater than two Bilinear MIP Maps or more than one Trilinear MIP Map would require multiple passes. The actual blending or composition of the MIP Maps is done in the raster engine. The texture engine provides the required texels including blending information. Flexible vertex format support allows multi-texturing because it makes it possible to pass more than one texture in the vertex structure.
5.4.2.14
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing processor load. There are several methods to generate environment maps such as spherical, circular and cubic. The GMCH supports cubic reflection mapping over spherical and circular since it is the best choice to provide real-time environment mapping for complex lighting and reflections. Cubic Mapping supports a texture map for each of the 6 cube faces. These can be generated by pointing a camera with a 90-degree field-of View in the appropriate direction. Per Vertex vectors (normal, reflection or refraction) are interpolated across the polygon and the intersection of these vectors with the cube texture faces are calculated. Texel values are then read from the intersection point on the appropriate face and filtered accordingly.
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5.4.2.15
Bump Mapping
The GMCH only supports embossed and dot product bump mapping, not environment bump mapping.
5.4.3
Raster Engine
The Raster Engine is where the color data such as fogging, specular RGB, texture map blending, etc. is processed. The final color of the pixel is calculated and the RGB value combined with the corresponding components resulting from the Texture Engine. These textured pixels are modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer tests are conducted which will determine whether the Frame and Depth Buffers will be updated with the new pixel values.
5.4.3.1
Texture Map Blending
Multiple Textures can be blended together in an iterative process and applied to a primitive. The GMCH allows up to four distinct or shared texture coordinates and texture maps to be specified onto the same polygon. Also, the GMCH supports a texture coordinate set to access multiple texture maps. State variables in multiple textures are bound to texture coordinates, texture map or texture blending.
5.4.3.2
Combining Intrinsic and Specular Color Components
The GMCH allows an independently specified and interpolated "specular RGB" attribute to be added to the post-texture blended pixel color. This feature provides a full RGB specular highlight to be applied to a textured surface, permitting a high quality reflective colored lighting effect not available in devices, which apply texture after the lighting components have been combined. If specular-add state variable is disabled, only the resultant colors from the map blending are used. If this state variable is enabled, the specular RGB color is added to the RGB values from the output of the map blending.
5.4.3.3
Color Shading Modes
The Raster Engine supports the flat and Gouraud shading modes. These shading modes are programmed by the appropriate state variables issued through the command stream. * Flat shading is performed by smoothly interpolating the vertex intrinsic color components (Red, Green, Blue), Specular (R, G, B), Fog, and Alpha to the pixel, where each vertex color has the same value. The setup engine substitutes one of the vertex's attribute values for the other two vertices attribute values thereby creating the correct flat shading terms. This condition is set up by the appropriate state variables issued prior to rendering the primitive. * Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (Red, Green, Blue). Specular (RGB), Fog, and Alpha to the pixel, where each vertex color has a different value. All the attributes can be selected independently to one of the shading modes by setting the appropriate value state variables.
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5.4.3.4
Color Dithering
Color Dithering in the GMCH helps to hide color quantization errors for 16-bit color buffers. Color Dithering takes advantage of the human eye's propensity to "average" the colors in a small area. Input color, alpha, and fog components are converted from 8-bit components to 5-bit or 6-bit component by dithering. Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not performed.
5.4.3.5
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects such as low visibility conditions in flight simulatortype games. It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate. Fog is simulated by attenuating the color of an object with the fog color as a function of distance, and the greater the distance, the higher the density (lower visibility for distant objects). There are two ways to implement the fogging technique: per Vertex (linear) fogging and per-pixel (non-linear) fogging. The per Vertex method interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel within the polygon. This method provides realistic fogging as long as the polygons are small. With large polygons (such as a ground plane depicting an airport runway), the per Vertex technique results in unnatural fogging. The GMCH supports both types of fog operations, vertex and per pixel or table fog. If fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. If fog is enabled, the incoming pixel color is blended with the fog color based on a fog coefficient on a per pixel basis using the following equation before sending to the destination blend unit.
5.4.3.6
Alpha Blending
Alpha Blending in the GMCH adds the material property of transparency or opacity to an object. Alpha blending combines a source pixel color and alpha component with a destination pixel color and alpha component. For example, a glass surface on top (source) of a red surface (destination) would allow much of the red base color to show through. Blending allows the source and destination color values to be multiplied by programmable factors and then combined via a programmable blend function. The combined and independent selection of factors and blend functions for color and alpha is supported.
5.4.3.7
Color Buffer Formats: (Destination Alpha)
The Raster Engine supports 8-bit, 16-bit, and 32-bit Color Buffer Formats. The 8-bit format is used to support planar YUV420 format, which is used only in Motion Compensation and Arithmetic Stretch format. The bit format of Color and Z is allowed to mix. The GMCH can support an 8-bit destination alpha in 32-bit mode. Destination alpha is supported in 16-bit mode in 1555 or 4444 format. The GMCH does not support general 3D rendering to 8bit surfaces. 8-bit destinations are supported for operations on planar YUV surfaces (e.g., stretch Blts) where each 8-bit color component is written in a separate pass. The GMCH also supports a mode where both U and V planar surfaces can be operated on simultaneously.
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The frame buffer of the GMCH contains at least two hardware buffers, the Front Buffer (display buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with (or be part of) the visible display surface, a separate (screen or window-sized) back buffer is typically used to permit double-buffered drawing. That is, the image being drawn is not visible until the scene is complete and the back buffer made visible or copied to the front buffer via a 2D BLT operation. Rendering to one buffer and displaying from the other buffer removes image tearing artifacts. Additionally, more than two back buffers (e.g., triple-buffering) can be supported.
5.4.3.8
Depth Buffer
The Raster Engine is able to read and write from this buffer and use the data in per fragment operations that determine resultant color and depth value of the pixel for the fragment are to be updated or not. Typical applications for entertainment or visual simulations with exterior scenes require far/near ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A 24bit Z-buffer provides 16 million Z Values as opposed to only 64 k with a 16-bit Z-buffer. With lower Z-resolution, two distant overlapping objects may be assigned the same Z Value. As a result, the rendering hardware may have a problem resolving the order of the objects, and the object in the back may appear through the object in the front. By contrast, when w (or eye-relative z) is used, the buffer bits can be more evenly allocated between the near and far clip planes in world space. The key benefit is that the ratio of far and near is no longer an issue, and allows applications to support a maximum range of miles, yet still get reasonably accurate depth buffering within inches of the eye point. The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit mode.
5.4.3.9
Stencil Buffer
The Raster engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform stencil testing. Stencil testing controls 3D drawing on a per pixel basis and conditionally eliminates a pixel on the outcome of a comparison between a stencil reference value and the value in the stencil buffer at the location of the source pixel being processed. They are typically used in multipass algorithms to achieve special effects, such as decals, outlining, shadows, and constructive solid geometry rendering. One of three possible stencil operations is performed when stencil testing is enabled. The stencil operation specifies how the stencil buffer is modified when a fragment passes or fails the stencil test. The selection of the stencil operation to be performed is based upon the result of the stencil test and the depth test. A stencil write mask is also included that controls the writing of particular bits into the stencil buffer. It selects between the destination value and the updated value on a perbit basis. The mask is 8-bit wide.
5.4.3.10
Projective Textures
The GMCH supports two simultaneous projective textures at full rate processing. These textures require three floating-point texture coordinates to be included in the FVF format. Projective textures enable special effects such as projecting spot light textures obliquely onto walls, etc.
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5.4.4
GMCH 2D Engine
The GMCH provides an extensive set of 2D instructions and 2D HW acceleration for block transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. The Stretch BLT engine is used to move source data to a destination that need not be the same size, with source transparency. Performing these common tasks in hardware reduces processor load, and thus improves performance.
5.4.4.1
256-Bit Pattern Fill and BLT Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*. The GMCH BLT Engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The term BLT refers to a block transfer of pixel data between system memory locations. The BLT engine can be used for the following: * Move rectangular blocks of data between system memory locations * Data Alignment * Perform logical operations (raster ops) The rectangular block of data does not change as it is transferred between system memory locations. Data to be transferred can consist of regions of system memory, patterns, or solid color fills. A pattern will always be 8x8 pixels wide and may be 8-bits, 16-bits, or 32-bits per pixel. The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8-bits, 16-bits, or 32-bits. BLTs can be either opaque or transparent. Opaque transfers, move the data specified to the destination. Transparent transfers compare destination color to source color and write according to the mode of transparency selected. Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source system memory location, the GMCH can specify which area in system memory to begin the BLT transfer. Hardware is included for all 256 raster operations (Source, Pattern, and Destination) defined by Microsoft, including transparent BLT. The GMCH has instructions to invoke BLT operations, permitting software to set up instruction buffers and use batch processing as described in the Instruction Processing Section. The GMCH can perform hardware clipping during BLTs.
5.4.4.2
Alpha Stretch BLT
The stretch BLT function can stretch source data in the X and Y directions to a destination larger or smaller than the source. Stretch BLT functionality expands a region of system memory into a larger or smaller region using replication and interpolation. The stretch BLT function also provides format conversion and data alignment.
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5.4.5
GMCH Planes and Engines
The GMCH display can be functionally delineated into Planes and Engines (Pipes and Ports). A plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces, which are rectangular system memory surfaces with a similar set of characteristics. They are also associated with a particular destination pipe. A pipe consists of a set of planes that will be combined and a timing generator. A port is the destination for the result of the pipe. Therefore, planes are associated with pipes and pipes are associated with ports.
5.4.5.1
Dual Pipe Independent Display Functionality
The display consists of two display pipes, A and B. Pipes have a set of planes that are assigned to them as sources. The analog display port may only use Pipe A or Pipe B, DVOB and DVO C port may use either Pipe A or Pipe B, and the LFP LVDS interface may only use Pipe B. This limits the resolutions available on a digital display when an analog CRT is active.
Table 42. Dual Display Usage Model
Display Pipe A CRT DVO B or DVO C or both CRT DVO B or DVO C or both CRT/DVO B or DVO C or both Display Pipe B LFP (Internal LVDS) CRT DVO B or DVO C or both (Simultaneous Scan) LFP (Internal LVDS) LFP (Internal LVDS)
5.4.6
Hardware Cursor Plane
The GMCH supports two hardware cursors. The cursor plane is one of the simplest display planes. With a few exceptions, has a fixed size of 64 x 64 and a fixed Z-order (top). In legacy modes, cursor can cause the display data below it to be inverted. In the alpha blend mode, true color cursor data can be alpha blended into the display stream. It can be assigned to either display pipe A or display pipe B and dynamically flipped from one to the other when both are running.
5.4.6.1
Cursor Color Formats
Color data can be in an indexed format or a true color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. The index can optionally specify that a cursor pixel be transparent or cause an inversion of the pixel value below it or one of two colors from the cursor palette. Blending of YUV or RGB data is only supported with planes that have data of the same format.
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5.4.6.2
Popup Plane (Second Cursor)
The popup plane is used for control functions in mobile applications. Only the hardware cursor has a higher Z-order precedence over the hardware icon. In standard modes (non VGA) either cursor A or cursor B can be used as a Popup Icon. For VGA modes, 32-bpp data format is not supported.
5.4.6.3
Popup Color Formats
Source color data for the popup is in an indexed format. Indexed data uses the entries in the fourentry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. Blending of color data is only supported with data of the same format.
5.4.7
Overlay Plane
The overlay engine provides a method of merging either video capture data (from an external Video Capture device) or data delivered by the processor, with the graphics data on the screen.
5.4.7.1
Multiple Overlays (Display C)
A single overlay plane and scalar is implemented. This overlay plane can be connected to the primary display, secondary display or in bypass mode. In the default mode, it appears on the primary display. The overlay may be displayed in a multi-monitor scenario for single-pipe simultaneous displays only. Picture-in-Picture feature is supported via software through the arithmetic stretch blitter.
5.4.7.2
Source/Destination Color/Chromakeying
Overlay source/destination chromakeying enables blending of the overlay with the underlying graphics background. Destination color-/chromakeying can be used to handle occluded portions of the overlay window on a pixel-by-pixel basis that is actually an underlay. Destination color keying supports a specific color (8-bit or 15-bit) mode as well as 32-bit alpha blending. Source color/chromakeying is used to handle transparency based on the overlay window on a pixel-by-pixel basis. This is used when "blue screening" an image to overlay the image on a new background later.
5.4.7.3
Gamma Correction
To compensate for overlay color intensity loss, the overlay engine supports independent gamma correction. This allows the overlay data to be converted to linear data or corrected for the display device when not blending.
5.4.7.4
YUV to RGB Conversion
The format conversion can be bypassed in the case of RGB source data.
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5.4.7.5
Color Control
Color control provides a method of changing the color characteristics of the pixel data. It is applied to the data while in YUV format and uses input parameters such as brightness, saturation, hue (tint) and contrast. This feature is supplied for the overlay only and works in YUV formats only.
5.4.7.6
Dynamic Bob and Weave
Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second. There are several schemes to de-interlace the video stream: line replication, vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the previous field and inserts them into the current field to construct the frame - this is known as weaving. This is the best solution for images with little motion; however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. Vertical filtering or "Bob" interpolates adjacent lines rather replicating the nearest neighbor. This is the best solution for images with motion however, it will have reduced spatial resolution in areas that have no motion and introduce jaggies. In absence of any other deinterlacing, these form the baseline and are supported by the GMCH.
5.4.8
Video Functionality
The GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV all format decode.
5.4.8.1
MPEG-2 Decoding
The GMCH MPEG2 Decoding supports Hardware Motion Compensation (HWMC). The GMCH can accelerate video decoding for the following video coding standards: * MPEG-2 support * MPEG-1: Full feature support * H.263 support * MPEG-4: Only supports some features in the simple profile. The GMCH HWMC interface is optimized for the Microsoft Direct VA* API. Hardware Video Acceleration API (HVA) is a generic DirectDraw* and DirectShow* interface supported in Windows 2000 and Windows 98 Millennium to provide video decoding acceleration. Direct VA is the open standard implementation of HVA, which is natively supported by the GMCH hardware.
5.4.8.2
Hardware Motion Compensation
The Hardware Motion Compensation (HWMC) process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directional) the resulting pixel colors from one or more reference pictures. The GMCH receives the video stream and implements Motion Compensation and subsequent steps in hardware. Performing Motion Compensation in hardware reduces the processor demand of software-based MPEG-2 decoding, and thus improves system performance.
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5.4.8.3
Sub-picture Support
Sub-picture is used for two purposes: Subtitles for movie captions, which are superimposed on a main picture, and for menus to provide some visual operation environments for the user. DVD allows movie subtitles to be recorded as sub-pictures. On a DVD disc, it is called "Subtitle" because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks for Subtitles, they can be used for various applications, for example, as Subtitles in different languages. There are two kinds of menus, the system menus and other In-Title menus. First, the system menus are displayed and operated at startup of or during the playback of the disc or from the stop state. Second, In-Title menus can be programmed as a combination of sub-picture and highlight commands to be displayed during playback of the disc. The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed is a composite between the two video stream pixels. The GMCH can utilize four methods when dealing with sub-pictures. This flexibility means that the GMCH can work with all sub-picture formats.
5.5
Display Interface
The GMCH has four dedicated display interfaces, the analog port, the LFP LVDS interface, and the DVO B/C interface. The DVO B and DVO C interface can support TV-out encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. The data that is sent out the display port is selected from one of the two possible sources; display pipe A or display pipe B.
5.5.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector.
5.5.1.1
Integrated RAMDAC
The display function contains a 350 MHz integrated 24-bit RAM-based Digital-to-Analog Converter (RAMDAC) that transforms up to 2048 x 1536 digital pixels from the graphics and video subsystems to a maximum pixel analog data for the CRT monitor at a maximum refresh rate of 75-Hz for the Intel 852GME GMCH. Three, 8-bit DACs provide the R, G, and B signals to the monitor.
5.5.1.2
DDC (Display Data Channel)
DDC is defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plug-and-play systems to be realized. Support for DDC 1 and 2 is implemented.
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5.5.2
5.5.2.1
Digital Display Interface
Dedicated LFP LVDS Interface
The GMCH has a dedicated ANSI/TIA/EIA -644-1995 Specification compliant dual channel LFP LVDS interface that can support TFT panel resolutions up to UXGA with a maximum pixel format of 18-bpp, and with SSC supported frequency range from 25 MHz to 112 MHz (single channel/dual channel). The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values are then "locked" into the registers to prevent unwanted corruption of the values. From that point on, the display modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The timing signals will remain stable and active through mode changes. These mode changes include VGA to VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes. The transmitter can operate in a variety of modes and supports several data formats. The serializer supports 6-bit or 8-bit color and single or dual channel operating modes. The display stream from the display pipe is sent to the LVDS transmitter port at the dot clock frequency, which is determined by the panel timing requirements. The output of LVDS is running at a fixed multiple of the dot clock frequency, which is determined by the mode of operation; single or dual channel. Depending on configuration and mode, a single channel can take 18 bits of RGB pixel data plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits of RGB plus 3 bits of timing control output on four differential data pair outputs. A dual channel interface converts 36 or 48 bits of color information plus the 3 bits of timing control and outputs it on six or eight sets of differential data outputs. This display port is normally used in conjunction with the pipe functions of panel scaling and 6-8bit dither. This display port is also used in conjunction with the panel power sequencing and additional associated functions. When enabled, the LVDS constant current drivers consume significant power. Individual pairs or sets of pairs can be selected to be powered down when not used. When disabled, individual or sets of pairs will enter a low power state. When the port is disabled all pairs enter a low power mode. The panel power sequencing can be set to override the selected power state of the drivers during power sequencing. For more details on using the GMCH's LFP LVDS interface for TFT Panel support, please refer to the Common Panel Interface Specification, Rev 1.6 for details on: * CPIS Supported Resolutions * CPIS DC/AC Specifications * CPIS Pin Lists and Connectors * CPIS EDID Table Outline * CPIS Reference EDID Formats (XGA at 60-Hz Refresh Rate) * Sample CPIS EDID DTD's (Primary Resolution at 60-Hz Refresh Rate) * Video Serialization Formats
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* References and External Standards
5.5.2.2
LVDS Interface Signals
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. There are two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel consists of 4-data pairs and a clock pair. The interface consists of a total of ten differential signal pairs of which eight are data and two are clocks. The phase locked transmit clock is transmitted in parallel with the data being sent out over the data pairs and over the LVDS clock pair. Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a throughput of up to 784-Mbps on each data output and up to 112-MP/s on the input. When using both channels, they each operate at the same frequency each carrying a portion of the data. The maximum pixel rate is increased to 224-MP/s but may be limited to less than that due to restrictions elsewhere in the circuit. The LVDS Port Enable bit enables or disables the entire LVDS interface. When the port is disabled, it will be in a low power state. Once the port is enabled, individual driver pairs will be disabled based on the operating mode. Disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0's output.
5.5.2.3
LVDS Data Pairs and Clock Pairs
The LVDS data and clock pairs are identical buffers and differ only in the use defined for that pair. The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals. The pixel bus data to serial data mapping options are specified elsewhere. A single or dual clock pair is used to transfer clocking information to the LVDS receiver. A serial pattern of "1100011" represents 1 cycle of the clock. There are two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel contains 1 clock pair and 4-data pair of low voltage differential swing signals. The diagram below shows a pair of LVDS signals and swing voltage.
Figure 10. LVDS Swing Voltage
NOTE: 1's and 0's are represented the differential voltage between the pair of signals.
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Figure 11. LVDS Clock and Data Relationship
LVDS Clock Pair
1
1
1
0
0
0
1
1
1
LVDS Data Pair
7th data
1st data
2nd data
3rd data
4th data
5th data
6th data
7th data
1st data
LVDS Clock and data
5.5.2.4
LVDS Pair States
The LVDS pairs can be put into one of five states: powered down tri-state, powered down Zero Volts, common mode, send zeros, or active. When in the active state, several data formats are supported. When in powered down state, the circuit enters a low power state and drives out 0 V or tri-states on both the output pins for the entire channel. The common mode tri-state is both pins of the pair set to the common mode voltage. The common mode state only occurs on B3, A3, or CLKB. These are the signals that optionally get used when driving either 18-bpp panels or dual channel with a single clock. When in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless of what the actual data is with the clock lines and timing signals sending the normal clock and timing data.
5.5.2.5
Single Channel versus Dual Channel Mode
Both single channel and dual channel modes are available to allow interfacing to either single or dual channel panel interfaces. This LVDS port can operate in single channel or dual channel mode. Dual channel mode uses twice the number of LVDS pairs and transfers the pixel data at twice the rate of the single channel. In general, one channel will be used for even pixels and the other for odd pixel data. The first pixel of the line is determined by the display enable going active and that pixel will be sent out channel A. All horizontal timings for active, sync, and blank will be limited to two pixel boundaries in the two channel modes.
5.5.2.6
LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with respect to the inter-channel skew.
5.5.2.7
LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data across the LVDS interface. The three operations that are controlled are the pixel rate, the load rate, and the IO shift rate. These are synchronized to each other and have specific ratios based on single channel or dual channel mode. If the pixel clock is considered the 1x rate, a 7x or 3.5x speed IO_shift clock is needed for the high speed serial outputs setting the data rate of the transmitters. The load clock will have either a 1x or .5x ratio to the pixel clock.
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5.5.2.8
SSC Support
The GMCH is designed to tolerate a 0.6%-2.5% down/center spread at a modulation rate range from 30-50 kHz triangle. By using an external SSC clock synthesizer to provide the 66 MHz reference clock into the GMCH Pipe B PLL, spectrally spread 7X, 3.5X, and 1X LVDS clocking is output from the GMCH Pipe B PLL.
5.5.2.9
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. In order to meet the panel power timing specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to control the timing sequencing function of the panel and the backlight power supplies.
5.5.2.9.1
Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The panel VDD power, the backlight on/off state and the LVDS clock and data lines are all managed by an internal power sequencer. A requested power-up sequence is only allowed to begin after the power cycle delay time requirement T4 is met. This is programmed in the Power Cycle Delay bits (Panel Power Cycle Delay and Reference Divider Register address offset 61210-61213h, bits 0-4).
Figure 12. Panel Power Sequencing
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Table 43. Display Configuration Space
Name Panel Power Sequence Timing Parameters Spec Name T1+T2 Vdd On to LVDS Active Panel Vdd must be on for a minimum time before the LVDS data stream is enabled. T5 Backlight LVDS data must be enabled for a minimum time before the backlight is turned on. TX Backlight State Backlight must be disabled for a minimum time before the LVDS data stream is stopped. T3 LVDS State Data must be off for a minimum time before the panel VDD is turned off. T4 Power cycle Delay When panel VDD is turned from On to Off, a minimum wait must be satisfied before the panel VDD is enabled again. Power Off LVDS Active Backlight on 200 ms From 0.1 Vdd To LVDS Active 0 60 ms Min Max Units
Backlight Off
LVDS off
X
X
ms
LVDS Off
Start power off
0
50
ms
Power On Sequence Start
400
X
ms
5.5.2.10
Back Light Inverter Control
The GMCH offers integrated PWM for TFT panel Backlight Inverter control. Other methods of control are specified in the Common Panel Interface Specification, Version 1.6. * PWM - based Backlight Brightness Control * SMBus-based Backlight Brightness Control * DBL (Display Brightness Link) -to- VDL (Video Data Link) Power Sequencing
5.5.2.11
Digital Display Channel - DVOB and DVOC
The GMCH has the capability to support additional digital display devices (e.g. TMDS transmitter, LVDS transmitter or TV-out encoder) through its digital video output port. DVO B and DVOC can each deliver a 165 MHz dot clock on their 12-bit interface or deliver a 330 MHz dot clock on a combined 24-bit interface.
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The digital display port consists of a digital data bus, VSYNC, HSYNC, and BLANK# signals. The data bus can operate in a 12-bit or 24-bit mode. Embedded sync information or HSYNC and VSYNC signals can optionally provide the basic timing information to the external device and the BLANK# signal indicates which clock cycles contain valid data. The BLANK# signal can be optionally selected to include the border area of the timing. The VSYNC and HSYNC signals can be disabled when embedded sync information is to be used or to support DPMS. SYNC polarity can be adjusted using the VGA polarity selection bits or the port configuration bits. Optionally a STALL signal can cause the next line of data to not be sent until the STALL signal is removed. Optionally the FIELD pin can indicate to the overlay which field is currently being displayed at the display device.
5.6
AGP Interface Overview
The GMCH/MCH supports 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers are 1.5 V drive/receive (buffers are not 3.3 Volt tolerant). The GMCH/MCH supports 2X/4X source synchronous clocking transfers for read and write data, and sideband addressing. The GMCH/MCH also supports 2X and 4X clocking for Fast Writes initiated from the GMCH/MCH (on behalf of the processor). AGP PIPE# or SBA[7:0] transactions to DRAM do not get snooped and are, therefore, not coherent with the processor caches. AGP FRAME# transactions to DRAM are snooped. AGP PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access from an AGP master to the hub interface is also not supported. Only the AGP FRAME memory writes from the hub interface are supported.
5.6.1
AGP Target Operations
As an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCH/MCH supports AGP cycles targeting interface to main memory only. The GMCH supports interleaved AGP PIPE#] and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions.
Table 44. Display Configuration Space
GMCH/MCH Host Bridge Max AGP Command C/BE[3:0]# Encoding Cycle Destination Main Memory The hub interface Main Memory The hub interface N/A N/A Main Memory Response as PCIx Target Low Priority Read Complete locally with random data; does not go to the hub interface High Priority Read Complete locally with random data; does not go to the hub interface No Response No Response Low Priority Write
Read
0000 0000
Hi-Priority Read
0001 0000
Reserved Reserved Write
0010 0011 0100
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GMCH/MCH Host Bridge Max AGP Command C/BE[3:0]# Encoding Cycle Destination The hub interface Main Memory The hub interface N/A N/A Main Memory The hub interface Hi-Priority Long Read 1001 Main Memory The hub interface Flush Reserved Fence Reserved Reserved Reserved 1010 1011 1100 1101 1110 1111 GMCH N/A GMCH N/A N/A N/A Response as PCIx Target Cycle goes to DRAM with BE's inactive; does not go to the hub interface High Priority Write Cycle goes to DRAM with BE's inactive; does not go to the hub interface No Response No Response Low Priority Read Complete locally with random data; does not go to the hub interface High Priority Read Complete locally with random data; does not go to the hub interface Complete with QW of Random Data No Response No Response - Flag inserted in GMCH request queue No Response No Response No Response
0100 Hi-Priority Write 0101 0101 Reserved Reserved Long Read 0110 0111 1000
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP cycle, the GMCH/MCH supports all the transactions targeted at main memory (summarized in the table above). The GMCH/MCH supports both normal and highpriority read and write requests. The GMCH/MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles are assumed not to require coherency management and all AGP initiator accesses to main memory using AGP PIPE# or SBA protocol are treated as nonsnoopable cycles. These accesses are directed to the AGP aperture in main memory that is programmed as either uncacheable (UC) memory or write combining (WC) in the processor's MTRRs.
5.6.2
AGP Transaction Ordering
The GMCH observes transaction ordering rules as defined by the AGP Interface Specification Rev 2.0.
5.6.3
AGP Signal Levels
The GMCH/MCH supports 1X/2X/4X data transfers using 1.5 V signaling levels.
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5.6.4
4X AGP Protocol
In addition to the 1X and 2X AGP protocol, the GMCH/MCH supports 4X AGP read and write data transfers and 4X sideband address generation. The 4X operation is compliant with the AGP 2.0 specification. The GMCH/MCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP Status Register. When DATA_RATE[2] of the AGP Command Register is set to 1 during system initialization, the GMCH/MCH performs AGP read/write data transactions using 4X protocol. This bit is not dynamic. Once this bit is set during initialization, the data transfer rate will not change. The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X data transfer protocol is identical to 1X/2X protocol. In 4X mode 16 bytes of data are transferred on every 66 MHz clock edge. The minimum throttleable block size remains four 66 MHz clocks, which means 64 bytes of data are transferred per block. Three additional signal pins are required to implement the 4X data transfer protocol. These signal pins are complementary data transfer strobes for the AD bus (2) and the SBA bus (1).
5.6.4.1
Fast Writes
The GMCH/MCH supports 2X and 4X Fast Writes from the GMCH/MCH to the graphics controller on AGP. The Fast Write operation is compliant with the AGP 2.0 specification. The GMCH/MCH will not generate Fast Back to Back (FB2B) cycles in 1X mode, but will generate FB2B cycles in 2X and 4X Fast Write modes. To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4 of the AGP Command Register), must be set to 1. Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the bits set in the AGP Command Register bits 2:0 (DATA_RATE). * If bit 2 of the AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4X strobing. * If bit 1 of AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2X strobing. * If bit 0 of AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using standard PCI protocol. Note that only one of the three DATA_RATE bits may be set by initialization software. This is summarized in the following table.
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Table 45. Fast Write Initialization
FWEN DATA_RATE [2] DATA_RATE [1] DATA_RATE [0] x 1 0 0 GMCH =>AGP Master Write Protocol 1X 1X 2X Strobing 4X Strobing
0 1 1 1
X 0 0 1
x 0 1 0
5.6.4.2
AGP FRAME# Transactions on AGP
The GMCH/MCH accepts and generates AGP FRAME# transactions on the AGP bus. The GMCH/MCH guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
GMCH/MCH Initiator and Target Operations
Table 54 summarizes GMCH/MCH target operation for AGP FRAME# initiators. The cycles can be either destined for main memory or the hub interface. Table 46. PCI Commands Supported by the GMCH/MCH When Acting as a FRAME# Target
GMCH/MCH PCI Command C/BE[3:0]# Encoding Cycle Destination N/A N/A N/A N/A N/A N/A Main Memory The hub interface Main Memory The hub interface N/A N/A N/A Response as A FRAME# Target No Response No Response No Response No Response No Response No Response Read No Response Posts Data No Response No Response No Response No Response
Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read
0000 0001 0010 0011 0100 0101 0110 0110
Memory Write
0111 0111
Reserved Reserved Configuration Read
1000 1001 1010
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GMCH/MCH PCI Command C/BE[3:0]# Encoding Cycle Destination N/A Main Memory The hub interface N/A Main Memory The hub interface Main Memory Response as A FRAME# Target No Response Read No Response No Response Read No Response Posts Data
Configuration Write Memory Read Multiple
1011 1100 1100
Dual Address Cycle Memory Read Line
1101 1110 1110
Memory Write and Invalidate
1111
1111
The hub interface
No Response
NOTE: N/A refers to a function that is not applicable.
As a target of an AGP FRAME# cycle, the GMCH/MCH only supports the following transactions: * Memory Read, Memory Read Line, and Memory Read Multiple. These commands are supported identically by the GMCH/MCH. The GMCH/MCH does not support reads of the hub interface bus from AGP. * Memory Write and Memory Write and Invalidate. These commands are aliased and processed identically. The GMCH/MCH does not support writes to the hub interface bus from AGP. * Other Commands. Other commands such as I/O R/W and Configuration R/W are not supported by the GMCH as a target and result in master abort. * Exclusive Access. The GMCH/MCH does not support PCI locked cycles as a target. * Fast Back-to-Back Transactions. GMCH/MCH as a target supports fast back-to-back cycles from an AGP FRAME# initiator. As an initiator of AGP FRAME# cycle, the GMCH/MCH only supports the following transactions: * Memory Read and Memory Read Line. GMCH/MCH supports reads from host to AGP. GMCH/MCH does not support reads from the hub interface to AGP. * Memory Read Multiple. This command is not supported by the GMCH/MCH as an AGP FRAME# initiator. * Memory Write. GMCH/MCH initiates AGP FRAME# cycles on behalf of the host or the hub interface. GMCH/MCH does not issue Memory Write and Invalidate as an initiator. GMCH/MCH does not support write merging or write collapsing. GMCH/MCH allows nonsnoopable write transactions from the hub interface to the AGP bus. * I/O Read and Write. I/O read and write from the host are sent to the AGP bus. I/O base and limit address range for AGP bus are programmed in AGP FRAME# configuration registers.
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All other accesses that do not correspond to this programmed address range are forwarded to the hub interface. * Exclusive Access. GMCH/MCH does not issue a locked cycle on the AGP bus on behalf of either the host or the hub interface. The hub interface and host locked transactions to AGP are initiated as unlocked transactions by the GMCH/MCH on the AGP bus. * Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1 Configuration Cycles. * Fast Back-to-Back Transactions. GMCH/MCH as an initiator does not perform fast back-toback cycles.
GMCH Retry/Disconnect Conditions
The GMCH generates retry/disconnect according to the AGP Specification rules when being accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-DRAM read cycle is retried by the GMCH, it is processed internally as a Delayed Transaction. The GMCH/MCH supports the Delayed Transaction mechanism on the AGP target interface for the transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI 2.1 Specification. The process of latching all information required to complete the transaction, terminating with Retry, and completing the request without holding the master in wait-states is called a Delayed Transaction. The GMCH/MCH latches the Address and Command when establishing a Delayed Transaction. The GMCH/MCH generates a Delayed Transaction on the AGP only for AGP FRAME# to DRAM read accesses. The GMCH/MCH does not allow more than one Delayed Transaction access from AGP at any time.
5.7
Power and Thermal Management
The Intel 852GME GMCH and Intel 852PM MCH are intended to be compliant with the following specifications and technologies: * APM Rev 1.2 * PCI Power Management Rev 1.0 * PC'99, Rev 1.0, PC'99A, and PC'01, Rev 1.0 * ACPI 1.0b and 2.0 support * ACPI S0, S1-M, S3, S4, S5, C0, C1, C2, C3 states * Internal Graphics Adapter D0, D1, D3 (Hot/Cold) * On Die Thermal sensor, enabling core and system memory write thermal throttling for prevention of catastrophic thermal conditions * External Thermal sensor input pin * Enabling SO-DIMM Thermal throttling
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* The GMCH also reduces I/O power dynamically, by disabling sense amps on input buffers, as well as tri-stating output buffers when possible * Dynamic Clock Power Down reduces power in all modes of operation * Enhanced Intel SpeedStep technology * Flat Panel Power Sequencing
5.8
General Description of Supported CPU States
C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is deasserted, and the processor core is active. The processor can service snoops and maintain cache coherency in this state. C1 (Auto Halt): The first level of power reduction occurs when the processor executes an AutoHalt instruction. This stops the execution of the instruction stream and reduces the processor's power consumption. The processor can service snoops and maintain cache coherency in this state. C2 (Stop Grant): To enter this low power state, STPCLK is asserted. The processor can still service snoops and maintain cache coherency in this state. C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The GMCH/MCH assumes that no hub interface cycles (except special cycles) will occur while the GMCH/MCH is in this state. The processor cannot snoop its caches to maintain coherency while in the C3 state. The GMCH/MCH will transition from the C0 state to the C3 state when software reads the Level 3 Register. This is an ACPI defined register but BIOS or APM (via BIOS) can use this facility when entering a low power state. The Host Clock PLL within the GMCH/MCH can be programmed to be shut off for increased power savings and the GMCH uses the DPSLP signal input for this purpose. C4 (Deeper Sleep): The C4 state appears to the GMCH/MCH as identical to the C3 state, but in this state the processor core voltage is lowered. There are no internal events in GMCH/MCH for the C4 state that differ from the C3 state.
5.9
General Description of ACPI States
Internal Graphics Adapter: * D0 Full on, display active * D1 Low power state, low latency recovery. No display, system memory retained * D3 Hot - All states lost other than PCI configuration. system memory lost (optionally) * D3 Cold - Power off CPU: * C0 Full On * C1 Auto Halt
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* C2 Stop Clock. Clock to CPU still running. Clock stopped to CPU core. * C3 Deep Sleep. Clock to CPU stopped. * C4 Deeper Sleep. Same as C3 with reduced voltage on the CPU. System States: * G0/S0 * G1/S2 * G1/S3 * G1/S4 * G2/S5 Full On * G1/S1-M Power On Suspend (POS). System Context Preserved Not supported. Suspend to RAM (STR). Power and context lost to chipset. Suspend to Disk (STD). All power lost (except wakeup on ICH4-M) Soft off. Total reboot.
5.10
Enhanced Intel SpeedStep(R) Technology Overview
With Enhanced Intel SpeedStep technology the processor core voltage changes and allows true CPU core frequency changes versus only clock throttling.
Table 47. Enhanced Intel SpeedStep(R) Technology Overview
CPU Mobile Intel Pentium 4 processor, Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology Additional lower voltages and frequencies OS based on CPU load demand, thermal control, or user event based CPU unavailability can be restricted to ~10 s (CPU dependent) by s/w
Benefit Over Non-power Managed CPU Transition Prompt CPU Availability
5.11
External Thermal Sensor Input
An External Thermal sensor with a serial interface may be placed next to DDR SDRAM SODIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed next to the SO-DIMM (or any other appropriate platform location) and connected to the External Thermal sensor. Intel advises that the External Thermal sensor contains some form of hysteresis, since none is provided by the GMCH/MCH hardware. The external sensor can be connected to the ICH4-M via the SMBus interface to allow programming and setup by BIOS software over the serial interface. The External sensor's output should include an Active-Low Open-Drain signal indicating an Over-Temp condition, which remains asserted for as long as the Over-Temp Condition exists, and deasserts when temperature has returned to within normal operating range. This External sensor output will be connected to the GMCH/MCH input (EXTTS_0) and will trigger a Preset Interrupt and/or Read-Throttle on a level-sensitive basis.
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Additional External Thermal sensor's outputs, for multiple sensors, can be wire-OR'ed together to allow signaling from multiple sensors located physically separately. Software can, if necessary, distinguish which SO-DIMM(s) is the source of the over-temp through the serial interface. However, since the SO-DIMM(s) will be located on the same system memory bus data lines, any GMCH/MCH-based Read Throttle will apply equally. Note: The use of external sensors that include an internal pull-up resistor on the open-drain Thermal trip output is discouraged. However, it may be possible, depending on the size of the pull-up and the voltage of the sensor.
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6
6.1
Electrical Characteristics
Absolute Maximum Ratings
Table 48 lists the Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the AC and DC tables. Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operating beyond the "operating conditions" is not recommended and extended exposure beyond "operating conditions" may affect reliability. Table 48. Absolute Maximum Ratings
Symbol Intel 852GM Only VCC VCCHL VCCASM 1.2 V Core Supply Voltage with respect to VSS 1.2 V Hub Interface Supply Voltage with respect to VSS 1.2 V DDR SDRAM System Memory Logic Supply Voltage (not connected to Core) with respect to VSS Power supply for the Host PLL, Power Supply for the Hub PLL, Power supply for the Display PLL A, Power supply for the Display PLL B, respectively -0.3 -0.3 -0.3 1.65 1.65 1.65 V V V Parameter Min Max Unit Notes
VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB
(R)
-0.3
1.65
V
Intel 852GME/852GMV GMCH and Intel 852PM MCH Only VCC VCCHL VCCASM 1.5 V Core Supply Voltage with respect to VSS 1.5 V Hub Interface Supply Voltage with respect to VSS 1.5 V DDR SDRAM System Memory Logic Supply Voltage (not connected to Core) with respect to VSS Power supply for the Host PLL, Power Supply for the Hub PLL, respectively -0.3 -0.3 -0.3 1.65 1.65 1.65 V V V
VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB
(R)
-0.3
1.65
V
Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH Common Tdie Tstorage Die Temperature under Bias Storage Temperature 0 -55 105 150 C C 1 2
(R)
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Symbol VCCADAC VCCDVO VCCDLVDS VCCTXLVDS VCCALVDS VCCSM VCCQSM VCCGPIO VTTLF
(R)
Parameter 1.5 V DAC Supply Voltage with respect to VSS 1.5 V Supply Voltage with respect to VSS 1.5 V LVDS Digital power supply 2.5 V LVDS Data/Clock Transmitter Supply Voltage with respect to VSS 1.5 V LVDS Analog Supply voltage with respect to VSS 2.5 V DDR SDRAM System Memory Data Buffers Supply Voltage with respect to VSS 2.5 V DDR SDRAM System Memory Clock Buffers Supply Voltage with respect to VSS 3.3 V GPIO Supply Voltage with respect to VSS AGTL+ buffer DC Input Voltage with respect to VSS
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max 1.65 1.65 1.65 3.25 1.65 3.25 3.25 3.6 1.55
Unit V V V V V V V V V
Notes
Intel 852GM/852GME/852GMV GMCH Only VCCADPLLA, VCCADPLLB Power supply for display PLL A and display PLL B -0.3 1.65 V
NOTES: 1. Functionality is not guaranteed for parts that exceed Tdie temperature above 105C. Full performance may be affected if the on-die thermal sensor is enabled. Please refer to the Montara Thermal Design Guide for supplementary details. 2. Possible damage to the GMCH/MCH may occur if the GMCH/MCH temperature exceeds 150C. Intel does not guarantee functionality for parts that have exceeded temperatures above 150C due to spec violation.
6.2
Thermal Characteristics
The Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH is designed for operation at die temperatures between 0C and 105C. The thermal resistance of the package is given in Table 49.
Table 49. Intel(R) 852GM/852GME/852GMV GMCH and Intel(R) 852PM MCH Package Thermal Resistance
Airflow Velocity in Meters/Second Parameter 0 m/s jt (C/Watt)** ja (C/Watt)** NOTE: ** Estimate 0.5 20.0 1 m/s 1.8 17.3
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6.3
Power Characteristics
Symbol Intel 852GM GMCH Only TDPTyp (max performance) Thermal Design Power 1.3 V Mobile Intel Pentium 4 processor AGTL+ Supply Current 1.05 V Mobile Intel Celeron processor AGTL+ Supply Current IVCCMax IVCCHL IVCCASM 1.2 V Core Supply Current 1.2 V Hub Interface Supply Current 1.2 V DDR SDRAM System Memory DLL Supply Current (DDR200/266 SDRAM ) 2.5 V DDR SDRAM System Memory Data Buffer Supply Current (DDR 200/266 SDRAM) ~ 3.2 0.80 0.69 1.29 0.09 0.24 W A A A A A 2 1
(R)
Table 50. Power Characteristics
Parameter Min Typ Max Unit Notes
IGTL
IVCCSM
1.6
A
Intel 852GME/852GMV GMCH Only TDPTyp (max performance) TDPTyp (max performance)
(R)
(R)
Thermal Design Power (Internal Graphics) Thermal Design Power (AGP Discrete Graphics)
~ 6.2 ~ 3.8
W W
1 1
Intel 852PM MCH Only TDPTyp (max performance)
(R)
Thermal Design Power (AGP Discrete Graphics)
(R)
~ 3.8
W
1
Intel 852GME/852GMV GMCH and Intel 852PM MCH Only IVCC(Internal Graphics) - Intel 852GME/ 852GMV Only IVCC(AGP Discrete Graphics) 852GME Only IGTL IVCC1_5_AGP IVCCHL IVCCASM AGTL+ Supply Current 1.5 V AGP Supply Current 1.5 V Hub Interface Supply Current 1.5 V DDR SDRAM System Memory DLL Supply Current (DDR266/333 SDRAM) 0.94 0.09 0.09 0.24 A A A A 1.5 V Core Supply Current 1.57 A 1.5 V Core Supply Current 2.54 A
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Symbol IVCCSM
Parameter 2.5 V DDR SDRAM System Memory Data Buffer Supply Current (DDR333 SDRAM)
(R)
Min
Typ
Max 2.00
Unit A
Notes
Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH Common IVCCDLVDS IVCCALVDS IVCCTXLVDS IVCCDAC IVCC1_5_DVO IVCCGPIO IVCCSM 1.5 V LVDS (Digital) Supply Current 1.5 V LVDS (Analog) Supply Current 2.5 V LVDS (I/O) Supply Current 1.5 V DAC Supply Current 1.5 V DVO Supply Current 3.3 V GPIO Supply Current 2.5 V DDR SDRAM System Memory Data Buffer Supply Current (DDR266 SDRAM) 2.5 V DDR SDRAM System Memory Interface Standby Supply Current 1.25V DDR SDRAM System Memory Interface Reference Voltage Supply Current DDR SDRAM System Memory Interface Reference Voltage (1.25V) Standby Supply Current DDR SDRAM System Memory Interface Resister Compensation Voltage (1.25 V) Supply Current DDR SDRAM System Memory Interface Resister Compensation Voltage (1.25 V) Standby Supply Current 0.04 0.07 0.05 0.07 0.09 0.02 1.70 A A A A A A A
(R)
ISUS_VCCSM ISMVREF_0
1 0.05
mA mA
ISUS_SMVREF_0
0.05
mA
ITTRC/RCOMP
40
mA
ISUS_TTRC
0
mA
NOTES: 1. This spec is the Thermal Design Power and is the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations in both hardware and software technology over the life of the component. It does not represent the expected power generated by a power virus. Studies by Intel indicate that no application will cause thermally significant power dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads that write but never read. Under realistic read/write conditions, this higher power workload can only be transient and is accounted in the Icc (max) spec. 2. IGTL for Host Interface for design with mobile Intel Celeron processor.
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6.4
Signal Groups
The signal description includes the type of buffer used for the particular signal:
Signal AGTL+ Description Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The GMCH/MCH integrates AGTL+ termination resistors. AGTL+ signals are "inverted bus" style where a low voltage represents a logical 1. DVO/AGP buffers (1.5 V tolerant) Compatible to Hub Interface 1.5 Stub Series Termination Logic compatible signals (2.5 V tolerant) Low Voltage TTL compatible signals (3.3 V tolerant) CMOS buffers (3.3 V tolerant) Low Voltage Differential Signal interface Analog signal interface Voltage reference signal
DVO/AGP Hub SSTL_2 LVTTL CMOS LVDS Analog Ref
Table 51. Signal Groups
Signal Group Signal Type Signals Notes
Host Interface Signal Groups (a) AGTL+ Input/Outputs AGTL+ Common Clock Outputs Analog/Ref Host Miscellaneous Signals AGTL+ Asynchronous Input ADS#, BNR#, BREQ0#,DBSY#, DRDY#, DINV[3:0]#, HA[31:3]#, HADSTB[1:0]#, HD[63:0]#,HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]#, HLOCK# BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]#, DPWR# HAVREF, HCCVREF, HDVREF[2:0], HXSWING, HYSWING, HXRCOMP, HYRCOMP HLOCK#, DPSLP#
(b)
(d)
(c)
DVO Signal Groups (e) (f) DVO Inputs DVO Outputs DVO 2 DDC/I C Input/Output DVOBCCLKINT, DVOCFLDSTL, DVOBCINTR#, DVOBFLDSTL, ADDID[7:0], DVODETECT DVOCD[11:0], DVOCHSYNC, DVOCVSYNC, DVOCBLANK#, DVOBD[11:0], DVOBHSYNC, DVOBVSYNC, DVOBBLANK# MI2CCLK, MI2CDATA, MDVICLK, MDVIDATA, MDDCDATA, MDDCCLK
(e),(f)
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Signal Group (g)
Signal Type
Signals
Notes
Analog/Ref DVO Miscellaneous Signals
GVREF, DVORCOMP
AGP Signal Groups (m1) AGP I/O AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], G_CBE[3:0]#, G_PAR, GST[2:0] PIPE#, SBA[7:0], RBF#, WBF#, SBSTB, SBSTB#, G_REQ# G_GNT#
(m2) (m3)
AGP Input AGP Output
LVDS Signal Groups (h) (i) LVDS LVDS Outputs Analog LVDS Miscellaneous IYAP[3:0], IYAM[3:0], IYBP[3:0], IYBM[3:0] LIBG
DAC Signal Groups (j) (k) CMOS/Analog DAC Outputs Analog/Ref DAC Miscellaneous RED, RED#, GREEN, GREEN#, BLUE, BLUE# REFSET
Hub Interface Signal Groups (l) (m) CMOS HI Inputs/Outputs Analog/Ref HI Miscellaneous HL[10:0], HLSTB, HLSTB# HLRCOMP, PSWING, HLVREF
DDR SDRAM Interface Signal Groups (n) (o) (p) SSTL_2 DDR Input/Outputs SSTL_2 DDR Outputs Analog/Ref DDR Miscellaneous SDQ[63:0], SDQS[7:0] SCS[3:0]#, SMA[12:0], SBA[1:0], SRAS#, SCAS#, SWE#, SCKE[3:0], SMAB[5,4,2,1], SDM[7:0] SMVREF_0, SMVSWINGH, SMVSWINGL, SMRCOMP
Clocks, Reset, and Miscellaneous Signal Groups (q) (r) CMOS Inputs CMOS Outputs CMOS DDC/I C Input/Outputs CMOS Clock Inputs
2
RSTIN#(3.3V), PWROK, EXTTS_0 AGPBUSY#,PANELVDDEN, PANELBKLTEN, PANELBKLTCTL, LCLKCTLA, LCLKCTLB, HSYNC, VSYNC DDCADATA, DDCPDATA, DDCACLK, DDCPCLK GCLKIN
(q),(r) (t)
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Signal Group (u) (w) (x) (z)
Signal Type
Signals
Notes
CMOS Clock Outputs 1.5 V Clock Inputs DVO Clock Outputs CMOS Low Voltage Differential Inputs LVTTL Inputs LVDS Clock Outputs
SCK[5:0], SCK[5:0]# DPMS DVOCCLK, DVOCCLK#, DVOBCLK, DVOBCLK# BCLK, BCLK#
(a1) (b1)
DREFCLK, DREFSSCLK ICLKAP, ICLKAM, ICLKBP, ICLKBM
I/O Buffer Supply Voltages/Grounds (c1) (d1) (e1) (f1) (g1) (g1) AGTL+ Power Supply 1.2/1.5 V Core 1.2/1.5 V Hub Interface 1.2/1.5 V PLL 2.5 V DDR SDRAM Supply 1.2/1.5V DDR SDRAM DLL Supply 1.5 V AGP/DVO Supply 1.5 V DAC Supply 3.3 V GPIO Supply 1.5 V LVDS Digital Supply 2.5 V LVDS Data/CLK Transmitter Supply 1.5 V LVDS Analog Supply Ground Power Supply VTTLF VCC VCCHL VCCAGPLL, VCCAHPLL, VCCADPLLA, VCCADPLLB VCCSM, VCCQSM VCCASM
(h1) (i1) (j1) (k1)
VCCDVO VCCADAC VCCGPIO VCCDLVDS
(k1)
VCCTXLVDS
(k1) (l1)
VCCALVDS VSS, VSSALVDS, VSSADAC
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6.5
DC Characteristics
Symbol Signal Group
(R)
Table 52. DC Characteristics
Parameter Min Nom Max Unit Notes
Supply Voltages (Intel 852GM GMCH Only) VCC VTTLF (d1) (c1) Core Voltage Active Range(AGTL+ Power Supply) HI I/O Supply Voltage PLL Supply Voltage 1.14 1.17 1.2 1.2(battery) 1.3(normal) 1.14 1.14 1.2 1.2 1.26 1.26 V V 1.26 1.43 V V
VCCHL VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB VCCASM
(e1) (f1)
(g1)
(R)
DDR I/O Supply Voltage
1.14
(R)
1.2
1.26
V
Supply Voltages (Intel 852GM GMCH with mobile Intel Celeron processor VCC VTTLF (d1) (c1) Core Voltage Active Range(AGTL+ Power Supply) HI I/O Supply Voltage PLL Supply Voltage 1.14 1.0 1.2 1.05 1.26 1.1 V V
VCCHL VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB VCCASM
(e1) (f1)
1.14 1.14
1.2 1.2
1.26 1.26
V V
(g1)
(R)
DDR I/O Supply Voltage
1.14
(R)
1.2
1.26
V
Supply Voltages (Intel 852GME/852GMV GMCH and Intel 852PM MCH Only) VCC VTTLF (Mobile Intel Pentium 4 Processor VTTLF (Mobile Prescott Processor VCCHL (d1) (c1) Core Voltage Active Range 1.425 1.05 1.5 1.2(Battery), 1.525(Normal) 1.575 1.55 V V
(c1)
Active Range
1.05
1.15(Battery), 1.325(Normal)
1.55
V
(e1)
HI I/O Supply Voltage
1.425
1.5
1.575
V
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Symbol
Signal Group (f1)
Parameter
Min
Nom
Max
Unit
Notes
VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB VCCASM
PLL Supply Voltage
1.425
1.5
1.575
V
(g1)
(R)
DDR I/O Supply Voltage
1.425
(R)
1.5
1.575
V
Supply Voltages (Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH Common) VCCSM VCCQSM VCCDVO VCCDLVDS VCCTXLVDS (h1) (k1) (k1) (g1) DDR I/O Supply Voltage AGP/DVO I/O Voltage Digital LVDS Supply Voltage Data/Clock Transmitter LVDS Supply Voltage Analog LVDS Supply Voltage DAC Supply Voltage CMOS Supply Voltage
(R) (R)
2.375
2.5
2.625
V
1.425 1.425 2.375
1.5 1.5 2.5
1.575 1.575 2.625
V V V
VCCALVDS VCCADAC VCCGPIO
(k1) (i1) (j1)
1.425 1.425 3.135
1.5 1.5 3.3
(R)
1.575 1.575 3.465
V V V
Reference Voltages (mobile Intel Pentium 4 processor and Celeron processor only ) HAVREF (d) Host Address and Reference Voltage Host Data Reference Voltage (0.66 x VTT) - 0.66 x VTT 2% (0.66x VTT) - 0.66 x VTT 2% (0.66 x VTT)+ 2% (0.66 x VTT)+ 2% (0.66 x VTT)+ 2% V
HDVREF[2:0]
(d)
V
HCCVREF
(d)
Host Common Clock (0.66 x VTT) - 0.66x VTT Voltage 2%
V
Reference Voltages (Mobile Pentium 4 processor Supporting Hyper-Threading Technology and Celeron D only) HAVREF (d) Host Address and Reference Voltage Host Data Reference Voltage (0.63 x VTT) - 0.63 x VTT 2% (0.63 x VTT) - 0.63 x VTT 2% (0.63 x VTT)+ 2% (0.63 x VTT)+ 2% (0.63 x VTT)+ 2% V
HDVREF[2:0]
(d)
V
HCCVREF
(d)
Host Common Clock (0.63 x VTT) - 0.63 x VTT Voltage 2%
V
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Symbol
Signal Group
Parameter
Min
Nom
Max
Unit
Notes
Reference Voltages (mobile Celeron processor only HAVREF (d) Host Address and Reference Voltage Host Data Reference Voltage (0.66 x 0.66 x VTTLF (0.66 x VTTLF)+ VTTLF) - 2% 2% (0.66 x 0.66 x VTTLF (0.66 x VTTLF)+ VTTLF) - 2% 2% V 2
HDVREF[2:0]
(d)
V
2
HCCVREF
(d)
Host Common Clock (0.66 x 0.66 x VTTLF (0.66 x Voltage VTTLF)+ VTTLF) - 2% 2%
V
2
Reference Voltages HXSWING HYSWING HLVREF SMVREF_0 GVREF (m) (p) (g) (d) Host Compensation Reference Voltage Hub Interface Reference Voltage DDR SDRAM Reference Voltage DVO Reference Voltage RCOMP Buffer Differential Amp Reference Voltage System Memory RCOMP Buffer Differential Amp Reference Voltage System Memory RCOMP Buffer Differential Amp Reference Voltage (0.33 x VTT) - 0.33 x VTT 2% 0.343 0.49 x VCCSM (0.50 x VCCDVO) - 2% 0.8 - 2% 0.350 0.50 x VCCSM 0.50 x VCCDVO 0.8 (0.33 x VTT) + 2% 0.357 0.51 x VCCSM (0.50 x VCCDVO ) + 2% 0.8 + 2% V
V V V
PSWING
(m)
V
SMVSWINGH
(p)
(VCCSM x VCCSM x 0.8 0.8) - 2%
(VCCSM x 0.8) + 2% (VCCSM x 0.2) + 2%
V
SMVSWINGL
(p)
(VCCSM x VCCSM x 0.2 0.2) - 2%
V
Host Interface(mobile Pentium 4 processor and Celeron processor only ) VIL_H VIH_H VOL_H (a), (c) (a),(c) (a),(b) Host AGTL+ Input Low Voltage Host AGTL+ Input High Voltage Host AGTL+ Output Low Voltage Host AGTL+ Output High Voltage Host AGTL+ Output Low Current VTT-0.1 -0.10 (0.66 x VTT) + 0.1 0 VTT (0.66xVT T)- 0.1 VTT + 0.1 (0.33 x VTT) + 0.1 VTT VTTmax / 0.75Rttmin V V V
VOH_H IOL_H
(a),(b) (a),(b)
V mA Rttmin=45
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Symbol
Signal Group (a),(c)
Parameter
Min
Nom
Max
Unit A
Notes
ILEAK_H
Host AGTL+ Input Leakage Current Host AGTL+ Input Capacitance Host AGTL+ Input Capacitance (common clock) 1 1 1.1 2
2
VOLCPAD CPCKG
(a),(c) (a),(c)
1.3 2.5
pF pF 1
Reference Voltages (Mobile Pentium 4 processor Supporting Hyper-Threading Technology and Celeron D only) VIL_H VIH_H VOL_H (a), (c) (a),(c) (a),(b) Host AGTL+ Input Low Voltage Host AGTL+ Input High Voltage Host AGTL+ Output Low Voltage Host AGTL+ Output High Voltage Host AGTL+ Output Low Current Host AGTL+ Input Leakage Current Host AGTL+ Input Capacitance Host AGTL+ Input Capacitance (common clock) 1 1 1.1 2 VTT-0.1 -0.10 (0.63 x VTT) + 0.1 0 VTT (0.63xVT T)- 0.1 VTT + 0.1 (0.33 x VTT) + 0.1 VTT VTTmax / 0.75Rttmin 2 V V
VOH_H IOL_H ILEAK_H
(a),(b) (a),(b) (a),(c)
V mA A Rttmin=45 VOLCPAD CPCKG
(a),(c) (a),(c)
1.3 2.5
pF pF 1
Reference Voltages (Mobile Celeron Processor only) VIL_H VIH_H VOL_H (a), (c) (a),(c) (a),(b) Host AGTL+ Input Low Voltage Host AGTL+ Input High Voltage Host AGTL+ Output Low Voltage Host AGTL+ Output High Voltage Host AGTL+ Output Low Current Host AGTL+ Input Leakage Current VTT-0.1 -0.10 (0.66 x VTT) + 0.1 0 VTT (0.66xVT T)- 0.1 VTT + 0.1 (0.33 x VTT) + 0.1 VTT VTTmax / 0.75Rttmin 2 V V V
VOH_H IOL_H ILEAK_H
(a),(b) (a),(b) (a),(c)
V mA A Rttmin=45 , 2 VOLDatasheet
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Electrical Characteristics
R
Symbol
Signal Group (a),(c) (a),(c)
Parameter
Min
Nom
Max
Unit
Notes
CPAD CPCKG
Host AGTL+ Input Capacitance Host AGTL+ Input Capacitance (common clock)
1 1
1.1 2
1.3 2.5
pF pF 1
DDR SDRAM Interface VIL(DC) VIH(DC) VIL(AC) VIH(AC) VOL VOH IOL IOH ILeak CPAD (n) (n) (n) (n) (o), (u) (o), (u) (o), (u) (o), (u) (n) (n) DDR SDRAM Input Low Voltage DDR SDRAM Input High Voltage DDR SDRAM Input Low Voltage DDR SDRAM Input High Voltage DDR SDRAM Output Low Voltage DDR SDRAM Output High Voltage DDR SDRAM Output Low Current DDR SDRAM Output High Current Input Leakage Current DDR SDRAM Input/Output Pin Capacitance DDR SDRAM Input/Output Pin Capacitance 4 5 -30 10 6 1.9 30 SMVREF _0 + 0.31 0.6 SMVREF _0+ 0.15 SMVREF _0 - 0.31 SMVREF _0 - 0.15 V V V V V V mA mA A pF
CPCKG
(n)
1
2
3
pF
1
1.5V AGP Interface VIL_A VIH_A VOL_A VOH_A IOL_A IOH_A (m1), (m2) (m1), (m2) (m1), (m3) (m1), (m3) (m1), (m3) (m1), (m3) AGP Input Low Voltage AGP Input High Voltage AGP Output Low Voltage AGP Output High Voltage AGP Output Low Current AGP Output High Current -6.9 1.275 6.9 GVREF+ 0.15 0.225 GVREF - 0.15 V V V V mA mA @0.15VD DQ @.85VD DQ
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Electrical Characteristics
R
Symbol
Signal Group (m1), (m2) (m1), (m2) (m1), (m2)
Parameter
Min
Nom
Max 10
Unit A pF pF
Notes
ILEAK_A CPAD CPCKG
AGP Input Leakage Current AGP Input Capacitance AGP Input Capacitance 3 1 3.5 2
04 3
1.5V DVO Interface: Functional Operating Range (VCC=1.5 V 5%) VIL_DVO VIH_DVO VOL_DVO VOH_DVO IOL_DVO IOH_DVO ILEAK_DVO C PAD CPCKG Hub Interface VIL_HI VIH_HI VIH_HI VOL_HI VOH_HI IOL_HI IOH_HI ILEAK_HI (l) (l) (l) (l) (l) (l) (l) (l) Hub Interface Input Low Voltage Hub Interface Input High Voltage Hub Interface Input High Voltage Hub Interface Output Low Voltage Hub Interface Output High Voltage Hub Interface Output Low Current Hub Interface Output High Current Hub Interface Input Leakage Current -1 10 0.75 1 HLVREF + 0.100 HLVREF + 0.200 0.05 HLVREF - 0.100 V V V V V mA mA A 2 IOL= 1 mA IOH = 1 mA @VOL_HI max @VOH_HI max 0Datasheet
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Electrical Characteristics
R
Symbol
Signal Group (l) (l)
Parameter
Min
Nom
Max
Unit
Notes
CPAD CPCKG
Hub Interface Input Capacitance Hub Interface Input Capacitance
2 1
3 2
4 3
pF pF
LVDS Interface: Functional Operating Range (VCC=2.5 V 5%) VOD (h), (b1) Differential Output Voltage Change in VOD between Complementary Output States Offset Voltage Change in VOS between Complementary Output States Output Short Circuit Current Output TRI-STATE Current -3.5 1 1.125 1.25 250 345 450 mV
VOD
(h), (b1)
50
mV
VOS
(h), (b1)
1.375
V
VOS
(h), (b1)
50
mV
IOs IOZ
(h), (b1) (h), (b1)
-10 10
mA A
Miscellaneous Signals VIL (q) Input Low Voltage (CMOS Inputs) VIH (q) Input High Voltage (CMOS Inputs) VOL VOH IOL IOH ILEAK (r) (r) (r) (r) (q) Output Low Voltage (CMOS Outputs) Output High Voltage (CMOS Outputs) Output Low Current (CMOS Outputs) Output High Current (CMOS Outputs) Input Leakage Current (CMOS Inputs) Input Capacitance (LVTTL Inputs) CPCKG (q) Input Capacitance (CMOS Inputs) 1 2 3 pF 1 1 1.25 -1 10 0.9 x VCC 1 0.1 x VCC V V mA mA A IOL= 1 mA IOH = 1 mA @VOL_HI max @VOH_HI max 0Cpad
(a1)
1.5
pF
222
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Electrical Characteristics
R
Symbol
Signal Group (q)
Parameter
Min
Nom
Max
Unit
Notes
CPAD
Input Capacitance (CMOS Inputs)
2.5
3.05
3.6
pF
CPCKG VIL
(q) (z)
Input Capacitance (CMOS Inputs) Input Low Voltage (CMOS Low Voltage Differential)
1 -0.15
2 0
3
pF V
1
VIH
(z)
Input High Voltage (CMOS Low Voltage Differential)
0.660
0.710
0.850
V
VCROSS
(z)
Crossing Voltage (CMOS Low Voltage Differential)
0.25
0.35
0.55
V
CPAD
(z)
Input Capacitance (CMOS Low Voltage Differential)
1
1.1
1.2
pF
CPCKG
(z)
Input Capacitance (CMOS Low Voltage Differential)
1
2
3
pF
1
VIL
(t), (a1)
Input Low Voltage (CMOS/LVTTL CLK Inputs)
0.8
V
VIH
(t), (a1)
Input High Voltage (CMOS/LVTTL CLK Inputs) Input Capacitance (CMOS CLK Inputs)
2.0
V
CPAD
(t)
1
1.25
1.5
pF
CPCKG
(t)
Input Capacitance (CMOS CLK Inputs)
1
2
3
pF
1
NOTES: 1. CPCKG is the trace capacitance in the GMCH/MCH package. 2. Hub Interface DC spec for VIH_HI is proposed for GMCH which have Hub VCC as 1.2 V nominal.
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Electrical Characteristics
R
6.5.1.1
DAC DC Characteristics
Table 53. DAC DC Characteristics: Functional Operating Range (VCCDAC = 1.5 V 5%)
Parameter
DAC Resolution Max Luminance (full-scale) Min Luminance LSB Current Integral Linearity (INL) Differential Linearity (DNL) Video channel-channel voltage amplitude mismatch Monotonicity Guaranteed 0 -1.0
Min
8 0.665
Typica l
Max
Units
Bits (1)
Notes
0.700 0.000 73.2
0.770
V V A
(1, 2, 4) white video level voltage (1, 3, 4) black video level voltage (4, 5) (1, 6) (1, 6) (7)
+2.0 +1.0 6
LSB LSB %
NOTES: 1. Measured at each R, G, B termination. According to the VESA Test Procedure - Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, and December 1, 2000). 2. Max steady-state amplitude 3. Min steady-state amplitude 4. Defined for a double 75- termination. 5. Set by external reference resistor value. 6. INL and DNL measured and calculated according to VESA Video Signal Standards. 7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).
Note: Reference the Intel(R) 852GM/852GME/852GMV and 852PM Chipset Platform Recommended Design and Debug Practices (RDDP), Rev. 0.8 for interconnect length specifications.
6.5.1.2
DAC Reference and Output Specifications
Table 54. DAC Reference and Output Specifications
Parameter
Reference resistor R,G,B termination resistor Video Filter Ferrite Bead Video Filter Capacitors
Min
124
Typical
127 75 75 3.3
Max
137
Units
pF
Notes
1% tolerance, 1/16 W (1) 1% tolerance, 1/16 W (3) @ 100- MHz (each R,G,B output) (3) Two capacitors per R,G,B output
NOTES: 1. VESA Video Signal Standard 2. Complement DAC channel output termination resistors are only required for differential video routing to the VGA connector. 3. Video filter capacitors and ferrite bead arranged in a PI configuration (one PI filter for R,G,B outputs).
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7
Testability
In the Intel 852GME GMCH and Intel 852PM MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. The XOR Chain test mode is used by product engineers during manufacturing and OEMs during board level connectivity tests. The main purpose of this test mode is to detect connectivity shorts between adjacent pins and to check proper bonding between I/O pads and I/O pins. Figure 13. XOR-Tree Chain
The algorithm used for in-circuit test is as follows: 1. Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain being tested. 2. Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
7.1
XOR Chain Differential Pairs
Table 55 provides differential signals in the XOR chains that must be treated as pairs. Pin1and Pin2 as shown need to always drive to the opposite value.
Table 55. Differential Signals in the XOR Chains
Pin1 DVOCCLK# HLSTB# DVOCCLK HLSTB Pin2 DVO XOR 2 HUB XOR XOR Chain
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Testability
R
7.2
XOR Chain Exclusion List
Table 56 provides a list of pins that are not included in the XOR chains (excluding all VCC/VSS/VTT). Note: Connectivity column is used to identify what need to be driven on that particular pin during XOR chain test mode.
Table 56. XOR Chains Exclusion List
Item# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IN IN IN IN/OUT IN IN IN Y3 W1 T2 U2 F1 D1 J11 B7 E8 C9 D9 C8 D8 A7 A8 D12 A10 B12 F12 B17 J17 B20 B18 J21 AD29 AE29 K21 Y28 Ball Pin/VHDL GCLKIN HLVREF HLRCOMP PSWING GVREF DVORCOMP PWROK DREFCLK REFSET BLUE BLUE# GREEN GREEN# RED RED# LVREFH LIBG LVBG LVREFL DREFSSCLK HDVREF[2] HXRCOMP HXSWING HDVREF[1] BCLK# BCLK HDVREF[0] HCCVREF I/O Type PLL CLK Analog Analog Analog Analog Analog CMOS PLL CLK Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog PLL CLK Analog Analog Analog Analog Diff Diff Analog Analog Voltage 3.3 1/3 VCCHL N/A N/A 1/2 VCCDVO N/A 3.3 3.3 N/A N/A N/A N/A N/A N/A N/A 1.1 N/A N/A 1.1 3.3 2/3 VTTLF N/A N/A 2/3 VTTLF 0.7 0.7 2/3 VTTLF 2/3 VTTLF Connectivity 0 0.4 N/A N/A 0.75 N/A N/A 0 N/A N/A N/A N/A N/A N/A N/A 1.1 N/A N/A 1.1 0 1.0 N/A N/A 1.0 0 0.7 1.0 1.0
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Testability
R
Item# 29 30 31 32 33 34
IN/OUT IN Y22 H28 K28 D28
Ball
Pin/VHDL HAVREF HYRCOMP HYSWING RSTIN# SMVREF_0 SMRCOMP
I/O Type Analog Analog Analog CMOS Analog Analog
Voltage 2/3 VTTLF N/A N/A 3.3 1/2 VCCSM N/A
Connectivity 1.0 N/A N/A N/A 1.25 N/A
AJ24 AB1
7.3
XOR Chain Connectivity/Ordering
The following tables contain the ordering for all of the Intel 852GME GMCH and Intel 852PM MCH XOR chains and pin to ball mapping information:
Table 57. XOR Mapping
XOR Chain DVO 1 XOR Out DVO IN/OUT Ball Pin/VHDL I/O Type Voltage
OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
AB5 T6 T5 T7 R3 R4 R6 R5 P2 P4 P3 P6 P5 N2 N3 M1 N5 M2 M5
SMA[12] RSVD RSVD MDDCDATA RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
SSTL_2 DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO N/A N/A N/A N/A N/A N/A N/A N/A
2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 N/A N/A N/A N/A N/A N/A N/A N/A
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19 20 21 22 23 24 25 26 27 28
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT OUT IN
M3 L2 P7 N6 M6 N7 L7 K7 B2 B3
DVOBCCLKINT RSVD MDDCCLK MI2CDATA MDVIDATA MDVICLK DVODETECT MI2CCLK RSVD RSVD XOR Chain DVO 2
DVO N/A DVO DVO DVO DVO DVO DVO N/A N/A
1.5 N/A 1.5 1.5 1.5 1.5 1.5 1.5 N/A N/A
XOR Out
DVO IN/OUT OUT
Ball AD5 L3 K1 L4 L5 K2 K5 K3 J2 J3 H2 J5 H1 J6 K6 H4 H3 H5 H6 G2 G3 D2 D3 F4
Pin/VHDL SMA[11] DVOCBLANK# DVOCD[1] RSVD DVOCVSYNC DVOCD[3] DVOCD[0] DVOCD[2] DVOCCLK# DVOCCLK DVOCD[6] DVOCD[5] DVOCD[7] DVOCD[4] DVOCHSYNC DVOCD[9] DVOCD[8] DVOCFLDSTL DVOCD[10] DVOBCINT# DVOCD[11] RSVD RSVD ADDID[5]
I/O Type SSTL_2 DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO DVO N/A N/A DVO 2.5 1.5 1.5 N/A 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 N/A N/A 1.5
Voltage
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT IN IN IN
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R
24 25 26 27 28 29 30 31 32 33 34 35 36
IN IN IN IN IN IN OUT IN OUT OUT IN IN IN
F5 F6 E2 E5 F3 F2 C2 E3 C3 C4 G5 G6 D5
ADDID[1] ADDID[7] ADDID[3] ADDID[0] RSVD RSVD RSVD ADDID[2] GST[1] GST[0] ADDID[4] ADDID[6] DPMS XOR Chain FSB 1
DVO DVO DVO DVO N/A N/A N/A DVO DVO DVO DVO DVO DVO
1.5 1.5 1.5 1.5 N/A N/A N/A 1.5 1.5 1.5 1.5 1.5 1.5
XOR Out
IN/OUT OUT
Ball AC19 D16 C16 G16 C17 E17 E16 F17 B19 E18 D18 C18 G17 C19 D20 E20 E19 G19 F19 G18 B21
Pin SMA[10] HD[62]# HD[60]# HD[58]# HD[55]# HD[61]# HD[59]# HD[56]# HD[57]# HDSTBP[3]# HDSTBN[3]# HD[63]# HD[51]# HD[54]# HD[52]# HD[50]# HD[49]# DINV[3]# HD[53]# HD[48]# HD[32]#
I/O Type SSTL_2 AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
Voltage
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
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R
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT OUT OUT OUT INOUT
C20 C23 B23 B22 B25 D22 C24 C21 E21 E22 D24 C25 F21 E24 E23 G21 F23 G20 M27 P28 AA22 AA26
HD[46]# HD[35]# HD[43]# HD[42]# DINV[2]# HD[36]# HD[34]# HD[47]# HDSTBP[2]# HDSTBN[2]# HD[39]# HD[37]# HD[45]# HD[38]# HD[41]# HD[33]# HD[44]# HD[40]# RS[2]# BPRI# DPWR# HADSTB[1]# XOR Chain FSB 2
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
XOR Out
IN/OUT OUT
Ball AC5 E25 B26 C26 B27 B28 G23 E26 D26 C27 G22 G24 SMA[9]
Pin
I/O Type SSTL_2 AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
Voltage
1 2 3 4 5 6 7 8 9 10 11
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
DINV[1]# HD[26]# HD[28]# HD[18]# HD[31]# HD[30]# HD[9]# HDSTBP[1]# HDSTBN[1]# HD[27]# HD[24]#
230
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R
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT OUT OUT OUT INOUT
C28 E27 F2 D27 G25 F25 H23 F28 K23 J23 H25 G27 K22 H26 G28 H27 J24 L23 K25 K27 J28 J25 K26 L24 L25 L27 J27 M28 N23 P26 T26
HD[25]# HD[20]# HD[17]# HD[23]# HD[21]# HD[16]# HD[19]# HD[22]# HD[11]# HD[14]# HD[10]# HD[12]# HD[0]# HD[15]# HD[5]# HD[1]# HD[9]# HD[7]# HD[2]# HDSTBP[0]# HDSTBN[0]# DINV[0]# HD[13]# HD[3]# HD[8]# HD[6]# HD[4]# DEFER# RS[0]# RS[1]# HADSTB[0]# XOR Chain FSB 3
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
XOR Out
IN/OUT OUT
Ball AC6 F15 Y23 SMA[8]
Pin
I/O Type SSTL_2 AGTL+ CMOS 2.5 1.5 1.5
Voltage
1 2
OUT IN
CPURST# DPSLP#
Datasheet
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R
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
INOUT INOUT INOUT INOUT IN INOUT OUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
N27 N28 N25 N24 P27 M23 M25 M26 L28 R28 P25 T28 R27 R23 R24 T27 U28 P23 T25 R25 V27 U27 V28 T23 U24 U23 V26 U25 V25 Y26 W28 W25 V23 W27 Y25 W24 Y27
HIT# HITM# BNR# DRDY# HLOCK# BREQ0# HTRDY# DBSY# ADS# HREQ[0]# HREQ[1]# HA[5]# HA[6]# HREQ[2]# HA[9]# HA[13]# HA[10]# HA[3]# HA[4]# HREQ[3]# HA[14]# HA[12]# HA[11]# HREQ[4]# HA[8]# HA[7]# HA[16]# HA[15]# HA[18]# HA[30]# HA[28]# HA[20]# HA[19]# HA[25]# HA[21] HA[23]# HA[26]#
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
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R
40 41 42 43 44 45
INOUT INOUT INOUT INOUT INOUT INOUT
Y24 AA27 W23 AB28 AB27 AA28
HA[17]# HA[22]# HA[24]# HA[31]# HA[29]# HA[27] XOR Chain GPIO
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
1.5 1.5 1.5 1.5 1.5 1.5
XOR Out
IN/OUT OUT
Ball AD7 G8 F8 C6 D6 F7 D7 C5 B4 H10 A5 B6 J9 G9 H9 SMA[7]
Pin
I/O Type SSTL_2 CMOS CMOS CMOS CMOS CMOS N/A CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 2.5 3.3 3.3 3.3 3.3 3.3 N/A 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
Voltage
1 2 3 4 5 6 7 8 9 10 11 12 13 14
OUT OUT OUT IN OUT IN INOUT INOUT OUT OUT INOUT OUT INOUT OUT
PANELBKLTCTL PANELBKLTEN LCLKCTLB EXTTS_0 AGPBUSY# RSVD DDCPDATA DDCPCLK HSYNC PANELVDDEN DDCACLK VSYNC DDCADATA LCLKCTLA XOR Chain HUB
XOR Out
IN/OUT OUT
Ball AD8 W2 W6 W7 V6 W3 V2 V5 V4 V3 U4 SMA[6] HL[4] HL[5] HL[7] HL[6] HLSTB
Pin
I/O Type SSTL_2 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 HL1.5 2.5 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2
Voltage
1 2 3 4 5 6 7 8 9 10
INOUT INOUT INOUT INOUT INOUT INOUT IN INOUT INOUT INOUT
HLSTB# Hl[9] HL[10] HL[3] HL[1]
Datasheet
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Testability
R
11 12 13
INOUT INOUT OUT
U3 U7 T3
HL[2] HL[0] HL[8] XOR Chain LVDS
HL1.5 HL1.5 HL1.5
1.2 1.2 1.2
XOR Out
IN/OUT OUT
Ball AD17 F10 E10 G10 G11 G12 H12 E11 E12 C11 C12 E13 D14 B13 C13 F14 G14 C14 C15 E14 E15 SMA[3]
Pin
I/O Type SSTL_2 LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
Voltage
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
ICLKBP ICLKBM IYBP[3] IYBM[3] IYBP[0] IYBM[0] IYBP[1] IYBM[1] IYBP[2] IYBM[2] ICLKAP ICLKAM IYAP[3] IYAM[3] IYAP[0] IYAM[0] IYAP[2] IYAM[2] IYAP[1] IYAM[1] XOR Chain SM1
XOR Out
DDR SDRAM IN/OUT OUT
Ball
Pin
I/O Type
Voltage
AD23 AE27 AD27 AF26 AG26 AC25 AD24
SCS[0]# SDQ[62] SDQ[63] SDQ[61] SDQ[60] SCS[3]# SDM[6]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5
1 2 3 4 5 6
INOUT INOUT INOUT INOUT OUT OUT
234
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Testability
R
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
INOUT OUT OUT INOUT OUT CLK CLK CLK CLK CLK CLK OUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INUT INOUT OUT OUT INOUT OUT
AH24 AD25 AC18 AH17 AD19 AC26 AB23 AA3 AC2 AB2 AC3 AH15 AF17 AF16 AG16 AE15 AH14 AE17 AD15 AE14 AG14 AH8 AE9 AC7 AG2 AE5
SDQS[6] SWE# SMA[0] SDQS[4] SDM[4] SCK[1] SCK[4] SCK[5] SCK[3] SCK[0] SCK[2] SDM[8] RSVD RSVD RSVD RSVD RSVD RSVD SDQS[8] RSVD RSVD SDQS[2] SDM[2] SCKE[0] SDQS[0] SDM[0] XOR Chain SM2
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 N/A N/A N/A N/A N/A N/A SSTL_2 N/A N/A SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 N/A N/A N/A N/A N/A N/A 2.5 N/A N/A 2.5 2.5 2.5 2.5 2.5
XOR Out
DDR SDRAM IN/OUT OUT
Ball
Pin
I/O Type
Voltage
AD26 AF28 AG28 AH27 AH28 AE26 AH26
SCS[1]# SDQ[59] SDQ[58] SDQS[7] SDM[7] SDQ[57] SDQ[56]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5
1 2 3 4 5 6
INOUT INOUT INOUT OUT INOUT INOUT
Datasheet
235
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Testability
R
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT OUT OUT OUT OUT OUT INOUT CLK CLK CLK CLK CLK CLK OUT OUT OUT OUT OUT OUT OUT INOUT OUT OUT OUT OUT INOUT OUT OUT
AH25 AG25 AF25 AE24 AH23 AF23 AE23 AG23 AE21 AD21 AD20 AD22 AC21 AC15 AC16 AB24 AB25 AB4 AA2 AD2 AD4 AD10 AD14 AD16 AD13 AF11 AC12 AC13 AE12 AH12 AD11 AC10 AE6 AH5 AC9 AB7
SDQ[51] SDQ[55] SDQ[54] SDQ[50] SDQ[49] SDQ[53] SDQ[48] SDQ[52] SDQS[5] SDM[5] SBA[1] SBA[0] SRAS# RCVENOUT# RCVENIN# SCK[4]# SCK[1]# SCK[5]# SCK[0]# SCK[3]# SCK[2]# SMAB[5] SMA[1] SMAB[1] SMA[2] SMAB[4] SMAB[2] SMA[5] SDQS[3] SDM[3] SMA[4] SCKE[3] SDM[1] SDQS[1] SCKE[2] SCKE[1]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
236
Datasheet
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Testability
R
XOR Chain SM 3 DDR SDRAM IN/OUT OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT Ball Pin I/O Type Voltage
XOR Out
AC22 AC24 AG22 AH22 AF22 AG20 AF20 AH21 AH19 AH20 AH16 AD18 AG19 AH18 AF19 AE18 AG17 AE20 AG13 AF14 AF13 AH13 AD12 AH10 AH11 AG11 AF10 AE11 AG10 AF8 AH9 AD9 AH7
SCS[2]# SCAS# SDQ[47] SDQ[43] SDQ[42] SDQ[41] SDQ[44] SDQ[46] SDQ[45] SDQ[40] SDQ[32] SDQ[36] SDQ[39] SDQ[38] SDQ[34] SDQ[37] SDQ[33] SDQ[35] SDQ[26] SDQ[27] SDQ[30] SDQ[31] SDQ[29] SDQ[24] SDQ[25] SDQ[28] SDQ[22] SDQ[23] SDQ[19] SDQ[16] SDQ[18] SDQ[21] SDQ[20]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
Datasheet
237
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Testability
R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
AG8 AF7 AG7 AE8 AH6 AF5 AD6 AH4 AG5 AH2 AF4 AG4 AH3 AF2 AD3 AE3 AE2
SDQ[17] SDQ[14] SDQ[10] SDQ[11] SDQ[15] SDQ[12] SDQ[8] SDQ[13] SDQ[9] SDQ[3] SDQ[2] SDQ[6] SDQ[7] SDQ[0] SDQ[4] SDQ[1] SDQ[5]
SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2
2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
7.4
VCC/VSS Voltage Groups
Name VCC Voltage Level 1.2 Ball out H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15, T17,U14,U16,W21,AA15,AA17,AA19 VCCADAC VCCDVO VCCASM VCCDLVDS VCCGPIO VCCHL VCCQSM VCCSM 1.5 1.5 1.2 1.5 3.3 1.2 2.5 2.5 A9,B9 E1,E4,E6,H7,J1,J4,J8,K9,L8,M4,M8,M9,N1,N8,P9,R8 AD1,AF1 B14,B15,G13,J13 A3,A4 U6,U8,V1,V7,V9,W5,W8,Y1 AJ6,AJ8 Y4,Y7,Y9,AA6,AA8,AA11,AA13,AB3,AB6,AB8,AB10, AB12,AB14,AB16,AB18,AB20,AB22,AC1,AC29,AF3, AF6,AF9,AF12,AF15,AF18,AF21,AF24,AF27,AF29, AG1,AG29,AJ5,AJ9,AJ13,AJ17,AJ21,AJ25 VCCTXLVDS 2.5 A12,B10,D10,F9
Table 58. Voltage Levels and Ball Out for Voltage Groups
238
Datasheet
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Testability
R
Name VTTHF VTTLF
Voltage Level 1.5 1.5 A22,A24,H29,M29,V29
Ball out
A18,A20,A26,F29,G15,H16,H18,H20,H22,J19,K29,L21, M22,N21,P22,R21,T22,U21,V22,Y29,AB29
VSS
0
A13,A17,A19,A21,A23,A25,A27,B5,B24,C1,C7,C10,C22,C29, D4,D11,D13,D15,D17,D19,D21,D23,D25,D28,E7,E9,E28,E29, F11,F13,F16,F18,F20,F22,F24,F27,G1,G4,G7,G26,G29,H8,H11, H13,H15,H17,H19,H21,H24,J7,J10,J12,J14,J16,J18,J20,J22,J26, J29,K4,K8,K24,L1,L6,L9,L22,L26,L29,M7,M21,M24,N4,N9,N13, N15,N17,N22,N26,N29,P8,P14,P16,P21,P24,R2,R7,R9,R13,R15, R17,R22,R26,T4,T8,T9,T14,T16,T21,T24,U1,U5,U9,U13,U15, U17,U22,U26,U29,V8,V21,V24,W4,W9,W22,W26,W29,Y5,Y6, Y8,Y21,AA1,AA4,AA7,AA10,AA12,AA14,AA16,AA18,AA20, AA21,AA23,AA24,AA25,AA29,AB9,AB11,AB13,AB15,AB17, AB19,AB21,AB26,AC4,AC8,AC11,AC14,AC17,AC20,AC23, AC27,AC28,AE1,AE4,AE7,AE10,AE13,AE16,AE19,AE22,AE25, AE28,AG3,AG6,AG9,AG12,AG15,AG18,AG21,AG24,AG27,AJ1, AJ3,AJ7,AJ10,AJ11,AJ12,AJ18,AJ20,AJ23,AJ26,AJ27
7.5
Power Sequence Recommendation
Power supplies on Intel 852GME GMCH and Intel 852PM MCH: FSB Core Hub Interface DVO DAC Internal Thermal Sensor LVDS DDR SDRAM GPIO VTT (Mobile Intel Pentium 4 processor, Intel Celeron processor) 1.5 V 1.5V 1.5 V (Intel 852GME GMCH Only) 1.5 V (Intel 852GME GMCH Only) 1.5 V 2.5 V and 1.5 V (Intel 852GME GMCH Only) 2.5 V 3.3 V 3.3 V
Datasheet
239
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Testability
R
Table 59. State of Power Planes in C/S States
C3 Power C0-C2 GV1/C4 SDRAM I/O HUB I/O DVO I/O FSB I/O CORE LVDS I/O GPIO On On On On On On On On On On On On On On On On On On On Off On On Off Off Off Off Off Off Off Off Off Off Off Off Off S1 S3 S4/S4+
For further details, refer to the Mobile Intel(R) Pentium(R) 4 Processor Datasheet, Mobile Intel(R) Pentium(R) 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Datasheet, Intel(R) Celeron(R) Processor Datasheet and the Intel(R) Celeron(R) D Processor on 90 nm process and in the 478-pin package Datasheet.
240
Datasheet
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Intel(R) 852GME GMCH and 852PM MCH Strap Pins
R
8
Intel(R) 852GME GMCH and 852PM MCH Strap Pins
Strapping Configuration Table
Pin Name LCLKCTLB Strap Description CPU Strap Configuration *Low=(default) High = Mobile Intel Pentium 4 processor /Intel Celeron processor HSYNC XOR Chain Test Low = Normal Ops (Default) High = XOR Test On VSYNC ALL Z Test Low = Normal Ops (Default) High = AllZ Test On DVODETECT
8.1
Table 60. Strapping Signals and Configuration
I/F Type GPIO Buffer Type OUT
GPIO
OUT
GPIO
OUT
DVO Select (If DVODETECT=0 during Reset, ADDID[7:0] is latched to the ADDID Register) DVO/AGP Select (Reserved)
Low = DVO (Default)
DVO
BI
GPAR
Low = DVO (Default) High = AGP No default
AGP
BI
GSBA[7:0]
8-bit ADD Identifier Straps SBA[0] = ID Bit_0 ... SBA[7] = ID Bit_7
AGP
IN
GST[2] Note: Intel 852GME GMCH Only
Clock Config: Bit_2
];
DVO
Hi-Z
FSB 400 = 0 FSB 533 = 1
External pull-ups/downs will be required on the board to enable the non-default state of the straps.
Datasheet
241
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Intel(R) 852GME GMCH and 852PM MCH Strap Pins
R
242
Datasheet
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Ballout and Package Information
R
9
Ballout and Package Information
Figure 14. Intel(R) 852GME GMCH Ballout Diagram (Top View)
Datasheet
243
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Ballout and Package Information
R
Table 61. Intel(R) 852GME GMCH Ballout Table
Row Column L E F E E G F G F L F AE AD C D N P F M B G B C M J E B G D Y AA N B 7 5 5 3 2 5 4 6 6 28 7 29 29 9 9 25 28 15 26 6 9 4 5 28 25 25 25 19 5 23 22 24 7 Signal Name DVODETECT ADDID[0] ADDID[1] ADDID[2] ADDID[3] ADDID[4] ADDID[5] ADDID[6] ADDID[7] ADS# AGPBUSY# BCLK BCLK# BLUE BLUE# BNR# BPRI# CPURST# DBSY# DDCACLK DDCADATA DDCPCLK DDCPDATA DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPMS DPSLP# DPWR# DRDY# DREFCLK Row Column B L M G P P R R M M R R P P N P N N M T T L J J K K H G K K J J H 17 2 3 2 3 4 3 5 1 5 6 4 6 5 5 2 2 3 2 6 5 3 3 2 5 1 6 3 3 2 6 5 2 Signal Name DREFSSCLK DVOBBLANK# DVOBCCLKINT DVOBCINTR# DVOBCLK DVOBCLK# DVOBD[0] DVOBD[1] DVOBD[10] DVOBD[11] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] DVOBD[8] DVOBD[9] DVOBFLDSTL DVOBHSYNC DVOBVSYNC DVOCBLANK# DVOCCLK DVOCCLK# DVOCD[0] DVOCD[1] DVOCD[10] DVOCD[11] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6]
244
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Ballout and Package Information
R
Row Column H H H H K L D D Y C D F U V U T V U V Y V V W Y AA W W W Y AA W AB P Y AB 1 3 4 5 6 5 1 6 3 8 8 1 28 28 27 27 27 25 26 24 25 23 25 25 27 24 23 27 27 28 28 27 23 26 28
Signal Name DVOCD[7] DVOCD[8] DVOCD[9] DVOCFLDSTL DVOCHSYNC DVOCVSYNC DVO_GRCOMP EXTTS_0 GCLKIN GREEN GREEN# GVREF HA[10]# HA[11]# HA[12]# HA[13]# HA[14]# HA[15]# HA[16]# HA[17]# HA[18]# HA[19]# HA[20]# HA[21]# HA[22]# HA[23]# HA[24]# HA[25]# HA[26]# HA[27]# HA[28]# HA[29]# HA[3]# HA[30]# HA[31]#
Row Column T T R U U R T AA Y Y K H H K G K J H F F B H K E G F D G C B G C E L G 25 28 27 23 24 24 26 26 22 28 22 27 25 23 27 26 23 26 25 26 27 23 25 27 25 28 27 24 28 26 22 26 26 24 23
Signal Name HA[4]# HA[5]# HA[6]# HA[7]# HA[8]# HA[9]# HADSTB[0]# HADSTB[1]# HAVREF HCCVREF HD[0]# HD[1]# HD[10]# HD[11]# HD[12]# HD[13]# HD[14]# HD[15]# HD[16]# HD[17]# HD[18]# HD[19]# HD[2]# HD[20]# HD[21]# HD[22]# HD[23]# HD[24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]# HD[3]# HD[30]#
Datasheet
245
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Ballout and Package Information
R
Row Column B B G C C D C E D J G E B B F F C C G E G E G D F C C F B G E L C E D 28 21 21 24 23 22 25 24 24 27 20 23 22 23 23 21 20 21 18 19 28 20 17 20 19 19 17 17 19 16 16 27 16 17 16
Signal Name HD[31]# HD[32]# HD[33]# HD[34]# HD[35]# HD[36]# HD[37]# HD[38]# HD[39]# HD[4]# HD[40]# HD[41]# HD[42]# HD[43]# HD[44]# HD[45]# HD[46]# HD[47]# HD[48]# HD[49]# HD[5]# HD[50]# HD[51]# HD[52]# HD[53]# HD[54]# HD[55]# HD[56]# HD[57]# HD[58]# HD[59]# HD[6]# HD[60]# HD[61]# HD[62]#
Row Column C L L J J C E D K D E E K J J N N U U V U V W W V W T V P W V W T R M 18 23 25 24 28 27 22 18 27 26 21 18 21 21 17 27 28 7 4 4 3 3 2 6 6 7 3 5 27 3 2 1 2 28 23
Signal Name HD[63]# HD[7]# HD[8]# HD[9]# HDSTBN[0]# HDSTBN[1]# HDSTBN[2]# HDSTBN[3]# HDSTBP[0]# HDSTBP[1]# HDSTBP[2]# HDSTBP[3]# HDVREF[0] HDVREF[1] HDVREF[2] HIT# HITM# HL[0] HL[1] HL[10] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HLOCK# HLSTB HLSTB# HLVREF HLRCOMP HREQ[0]# BREQ0#
246
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Ballout and Package Information
R
Row Column P R R T H M B B H K D E E F G E C C F E C B H E C G G E C G H C A P T 25 23 25 23 10 25 20 18 28 28 14 13 10 10 14 15 15 13 14 14 14 13 12 12 12 11 12 11 11 10 9 6 10 7 7
Signal Name HREQ[1]# HREQ[2]# HREQ[3]# HREQ[4]# HSYNC HTRDY# HXRCOMP HXSWING HYRCOMP HYSWING ICLKAM ICLKAP ICLKBM ICLKBP IYAM[0] IYAM[1] IYAM[2] IYAM[3] IYAP[0] IYAP[1] IYAP[2] IYAP[3] IYBM[0] IYBM[1] IYBM[2] IYBM[3] IYBP[0] IYBP[1] IYBP[2] IYBP[3] LCLKCTLA LCLKCTLB LIBG MDDCCLK MDDCDATA
Row Column N M K N AJ AH B A AJ A AA AJ AJ A AH B G F A U J A A E N P M AD F D B AA L C F 7 6 7 6 29 29 29 29 28 28 9 4 2 2 1 1 8 8 5 2 11 7 8 8 23 26 27 28 12 12 12 5 4 4 3
Signal Name MDVICLK MDVIDATA MI2CCLK MI2CDATA NC NC NC NC NC NC NC NC NC NC NC NC PANELBKLTCTL PANELBKLTEN PANELVDDEN PSWING PWROK RED RED# REFSET RS[0]# RS[1]# RS[2]# RSTIN# RSVD RSVD RSVD RSVD GCBE#[2] GST[0] GSBSTB#
Datasheet
247
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Ballout and Package Information
R
Row Column D C B F D C B AD AD AC AB AA AC AB AC AD AC AD AB AB AA AB AC AB AC AC AD AD AC AC AE AE AE AH AD 3 3 3 2 2 2 2 22 20 24 2 2 26 25 3 4 2 2 23 24 3 4 7 7 9 10 23 26 22 25 5 6 9 12 19
Signal Name GRBF# GST[1] GREQ# GSBSTB GWBF# GST[2] GGNT# SBA[0] SBA[1] SCAS# SCK[0] SCK[0]# SCK[1] SCK[1]# SCK[2] SCK[2]# SCK[3] SCK[3]# SCK[4] SCK[4]# SCK[5] SCK[5]# SCKE[0] SCKE[1] SCKE[2] SCKE[3] SCS[0]# SCS[1]# SCS[2]# SCS[3]# SDM[0] SDM[1] SDM[2] SDM[3] SDM[4]
Row Column AD AD AH AH AF AE AG AE AF AH AF AH AF AG AH AG AF AH AD AF AE AH AH AG AF AG AD AH AF AH AH AG AF AE AD 21 24 28 15 2 3 7 8 5 4 7 6 8 8 9 10 4 7 9 10 11 10 11 13 14 11 12 2 13 13 16 17 19 20 18
Signal Name SDM[5] SDM[6] SDM[7] SDM[8] SDQ[0] SDQ[1] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17] SDQ[18] SDQ[19] SDQ[2] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[3] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36]
248
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Ballout and Package Information
R
Row Column AE AH AG AD AH AG AF AH AF AH AH AG AE AH AE AE AH AG AF AF AG AH AE AG AF AG AG AF AE AD AG AE AE AG AH 18 18 19 3 20 20 22 22 20 19 21 22 23 23 2 24 25 23 23 25 25 26 26 28 28 4 26 26 27 27 14 14 17 16 14
Signal Name SDQ[37] SDQ[38] SDQ[39] SDQ[4] SDQ[40] SDQ[41] SDQ[42] SDQ[43] SDQ[44] SDQ[45] SDQ[46] SDQ[47] SDQ[48] SDQ[49] SDQ[5] SDQ[50] SDQ[51] SDQ[52] SDQ[53] SDQ[54] SDQ[55] SDQ[56] SDQ[57] SDQ[58] SDQ[59] SDQ[6] SDQ[60] SDQ[61] SDQ[62] SDQ[63] SDQ[64] SDQ[65] SDQ[66] SDQ[67] SDQ[68]
Row Column AE AH AF AF AD AG AG AA T P U R N AA T P J U R N H T P B A A B Y D A AF AD B B J 15 3 16 17 6 5 2 17 17 17 16 16 16 15 15 15 15 14 14 14 14 13 13 9 9 6 16 2 29 11 1 1 15 14 13
Signal Name SDQ[69] SDQ[7] SDQ[70] SDQ[71] SDQ[8] SDQ[9] SDQS[0] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCADAC VCCADAC VCCADPLLA VCCADPLLB VCCAGPLL VCCAHPLL VCCALVDS VCCASM VCCASM VCCDLVDS VCCDLVDS VCCDLVDS
Datasheet
249
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Ballout and Package Information
R
Row Column G P M K R N M L J H E M J E N J E A A V W U V U W Y V AJ AJ AG AF AC AF AJ AF 13 9 9 9 8 8 8 8 8 7 6 4 4 4 1 1 1 4 3 9 8 8 7 6 5 1 1 8 6 29 29 29 27 25 24
Signal Name VCCDLVDS VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCGPIO VCCGPIO VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCQSM VCCQSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM
Row Column AB AJ AF AB AF AB AJ AB AF AB AJ AA AF AB AA AB AJ AF Y AB AA Y AF AB AA AJ Y AF AB AG AC A D B F 22 21 21 20 18 18 17 16 15 14 13 13 12 12 11 10 9 9 9 8 8 7 6 6 6 5 4 3 3 1 1 12 10 10 9
Signal Name VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCTXLVDS VCCTXLVDS VCCTXLVDS VCCTXLVDS
250
Datasheet
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Ballout and Package Information
R
Row Column AA W U N L J G E C AE AC E D AJ AG AC F A AJ AB W U R N L J G AE AA D A AG AA V T 29 29 29 29 29 29 29 29 29 28 28 28 28 27 27 27 27 27 26 26 26 26 26 26 26 26 26 25 25 25 25 24 24 24 24
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column P M K H F B AJ AC AA D A AE W U R N L J F C AG AB AA Y V T P M H D A AJ AC AA J 24 24 24 24 24 24 23 23 23 23 23 22 22 22 22 22 22 22 22 22 21 21 21 21 21 21 21 21 21 21 21 20 20 20 20
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column F AE AB H D A AJ AG AA J F AC AB U R N H D A AE AA T P J F AG AB U R N H D AC AA T 20 19 19 19 19 19 18 18 18 18 18 17 17 17 17 17 17 17 17 16 16 16 16 16 16 15 15 15 15 15 15 15 14 14 14
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column P J AE AB U R N H F D A AJ AG AA J AJ AC AB H F D AJ AE AA J C AG AB W U T R N L E 14 14 13 13 13 13 13 13 13 13 13 12 12 12 12 11 11 11 11 11 11 10 10 10 10 10 9 9 9 9 9 9 9 9 9
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column AC Y V T P K H AJ AE AA R M J G E C AG Y L Y U B AE AC AA W T N K G D AJ AG R AJ 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 6 6 6 5 5 5 4 4 4 4 4 4 4 4 4 3 3 2 1
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column AE AA U L G C B B J V M H A A AB Y K F A V T P M H U B B L M G P P R R M 1 1 1 1 1 1 8 11 9 29 29 29 24 22 29 29 29 29 26 22 22 22 22 22 21 7 17 2 3 2 3 4 3 5 1
Signal Name VSS VSS VSS VSS VSS VSS VSSADAC VSSALVDS VSYNC VTTHF VTTHF VTTHF VTTHF VTTHF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF DREFCLK DREFSSCLK DVOBBLANK# DVOBCCLKINT DVOBCINTR# DVOBCLK DVOBCLK# DVOBD[0] DVOBD[1] DVOBD[10]
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Row Column M R R P P N P N N M T T L J J K K H G K K J AB T T R U U R T AA Y Y K H 5 6 4 6 5 5 2 2 3 2 6 5 3 3 2 5 1 6 3 3 2 6 28 25 28 27 23 24 24 26 26 22 28 22 27
Signal Name DVOBD[11] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] DVOBD[8] DVOBD[9] DVOBFLDSTL DVOBHSYNC DVOBVSYNC DVOCBLANK# DVOCCLK DVOCCLK# DVOCD[0] DVOCD[1] DVOCD[10] DVOCD[11] DVOCD[2] DVOCD[3] DVOCD[4] HA[31]# HA[4]# HA[5]# HA[6]# HA[7]# HA[8]# HA[9]# HADSTB[0]# HADSTB[1]# HAVREF HCCVREF HD[0]# HD[1]#
Row Column H K G K J H F F B H K E G F D G C B G C E L G L L J J C E D K D E E K 25 23 27 26 23 26 25 26 27 23 25 27 25 28 27 24 28 26 22 26 26 24 23 23 25 24 28 27 22 18 27 26 21 18 21
Signal Name HD[10]# HD[11]# HD[12]# HD[13]# HD[14]# HD[15]# HD[16]# HD[17]# HD[18]# HD[19]# HD[2]# HD[20]# HD[21]# HD[22]# HD[23]# HD[24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]# HD[3]# HD[30]# HD[7]# HD[8]# HD[9]# HDSTBN[0]# HDSTBN[1]# HDSTBN[2]# HDSTBN[3]# HDSTBP[0]# HDSTBP[1]# HDSTBP[2]# HDSTBP[3]# HDVREF[0]
254
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Row Column J J N N U U V U V W W V W T V P W V W T R M P R N AJ AH B A AJ A AA AJ AJ A 21 17 27 28 7 4 4 3 3 2 6 6 7 3 5 27 3 2 1 2 28 23 25 23 6 29 29 29 29 28 28 9 4 2 2
Signal Name HDVREF[1] HDVREF[2] HIT# HITM# HL[0] HL[1] HL[10] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HLOCK# HLSTB HLSTB# HLVREF HLRCOMP HREQ[0]# BREQ0# HREQ[1]# HREQ[2]# MI2CDATA NC NC NC NC NC NC NC NC NC NC
Row Column AH B G F A U J A A E N P M AD F D B AA L C F D C B F AE AG AE AF AH AF AH AF AG AH 1 1 8 8 5 2 11 7 8 8 23 26 27 28 12 12 12 5 4 4 3 3 3 3 2 3 7 8 5 4 7 6 8 8 9
Signal Name NC NC PANELBKLTCTL PANELBKLTEN PANELVDDEN PSWING PWROK RED RED# REFSET RS[0]# RS[1]# RS[2]# RSTIN# RSVD RSVD RSVD RSVD GCBE#[2] GST[0] GSBSTB# GRBF# GST[1] GREQ# GSBSTB SDQ[1] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17] SDQ[18]
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Row Column AG AF AH AD AF AE AH AH AG AF AG AD AH AF AH AH AG AF AE AD AE AH AG AD AH AG AH AH AE AH AE AH AH AD AC 10 4 7 9 10 11 10 11 13 14 11 12 2 13 13 16 17 19 20 18 18 18 19 3 20 20 5 8 12 17 21 24 27 15 18
Signal Name SDQ[19] SDQ[2] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[3] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[4] SDQ[40] SDQ[41] SDQS[1] SDQS[2] SDQS[3] SDQS[4] SDQS[5] SDQS[6] SDQS[7] SDQS[8] SMA[0]
Row Column AD AC AD AB AD AD AD AC AD AD AC AC AD AC AF AD AB AJ AJ AJ AC AC AC D AD W AA J H E M J E N J 14 19 5 5 13 17 11 13 8 7 6 5 16 12 11 10 1 24 19 22 21 16 15 7 25 21 19 8 7 6 4 4 4 1 1
Signal Name SMA[1] SMA[10] SMA[11] SMA[12] SMA[2] SMA[3] SMA[4] SMA[5] SMA[6] SMA[7] SMA[8] SMA[9] SMAB[1] SMAB[2] SMAB[4] SMAB[5] SMRCOMP SMVREF_0 SMVSWINGH SMVSWINGL SRAS# RCVENIN# RCVENOUT# RSVD SWE# VCC VCC VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO
256
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Row Column E A A V W U V U W Y V AJ AJ AG AF AC AF AJ AF AB AJ AF AB AF AB AJ AB AF AC E D AJ AG AC F 1 4 3 9 8 8 7 6 5 1 1 8 6 29 29 29 27 25 24 22 21 21 20 18 18 17 16 15 28 28 28 27 27 27 27
Signal Name VCCDVO VCCGPIO VCCGPIO VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCQSM VCCQSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VSS VSS VSS VSS VSS VSS VSS
Row Column A AJ AB W U R N L J G AE AA D A AG AA V T P M K H F B AJ AC AA D A AB U R N H D 27 26 26 26 26 26 26 26 26 26 25 25 25 25 24 24 24 24 24 24 24 24 24 24 23 23 23 23 23 17 17 17 17 17 17
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column A AE AA T P J F AG AB U R N H D AC AA T P J AE AB U R N H F D A AJ AG E C AG Y L 17 16 16 16 16 16 16 15 15 15 15 15 15 15 14 14 14 14 14 13 13 13 13 13 13 13 13 13 12 12 7 7 6 6 6
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column Y U B AE AC AA W T N K G D AJ AG R AJ AE AA U L G C B B J V M H A A AB R N L H 5 5 5 4 4 4 4 4 4 4 4 4 3 3 2 1 1 1 1 1 1 1 8 11 9 29 29 29 24 22 29 21 21 21 20
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSADAC VSSALVDS VSYNC VTTHF VTTHF VTTHF VTTHF VTTHF VTTLF VTTLF VTTLF VTTLF VTTLF
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Row Column A J H 20 19 18
Signal Name VTTLF VTTLF VTTLF
Row Column A H G 18 16 15
Signal Name VTTLF VTTLF VTTLF
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Figure 15. Intel(R) 852PM MCH Ballout Diagram (Top View)
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
NC
NC
VSS
VSS
VCCSM
SMVREF _0
VSS
SMVSWI VCCSM NGL
VSS
SMVSWI NGH
VSS
VCCSM
VCCSM
VSS
VSS
VSS
VCCSM
VCCQS M
VSS
VCCQS VCCSM M
NC
VSS
NC
VSS
AJ
NC
SDM[7] SDQS[7] SDQ[56] SDQ[51] SDQS[6] SDQ[49] SDQ[43] SDQ[46] SDQ[40] SDQ[45] SDQ[38] SDQS[4] SDQ[32] SDM[8] SDQ[68] SDQ[31] SDM[3] SDQ[25] SDQ[24] SDQ[18] SDQS[2] SDQ[20] SDQ[15] SDQS[1] SDQ[13] SDQ[7]
SDQ[3]
NC
AH
VCCSM SDQ[58]
VSS
SDQ[60] SDQ[55]
VSS
SDQ[52] SDQ[47]
VSS
SDQ[41] SDQ[39]
VSS
SDQ[33] SDQ[67]
VSS
SDQ[64] SDQ[26]
VSS
SDQ[28] SDQ[19]
VSS
SDQ[17] SDQ[10]
VSS
SDQ[9]
SDQ[6]
VSS
SDQS[0] VCCSM
AG
VCCSM SDQ[59] VCCSM SDQ[61] SDQ[54] VCCSM SDQ[53] SDQ[42] VCCSM SDQ[44] SDQ[34] VCCSM SDQ[71] SDQ[70] VCCSM SDQ[27] SDQ[30] VCCSM SMAB[4] SDQ[22] VCCSM SDQ[16] SDQ[14] VCCSM SDQ[12] SDQ[2]
VCCSM SDQ[0]
VCCAS M
AF
BCLK
VSS
SDQ[62] SDQ[57]
VSS
SDQ[50] SDQ[48]
VSS
SDQS[5] SDQ[35]
VSS
SDQ[37] SDQ[66]
VSS
SDQ[69] SDQ[65]
VSS
SDQS[3] SDQ[23]
VSS
SDM[2] SDQ[11]
VSS
SDM[1]
SDM[0]
VSS
SDQ[1]
SDQ[5]
VSS
AE
BCLK#
RSTIN# SDQ[63] SCS[1]#
SWE#
SDM[6] SCS[0]#
SBA[0]
SDM[5]
SBA[1]
SDM[4] SDQ[36] SMA[3] SMAB[1] SDQS[8] SMA[1]
SMA[2] SDQ[29] SMA[4] SMAB[5] SDQ[21] SMA[6]
SMA[7]
VCCAS SDQ[8] SMA[11] SCK[2]# SDQ[4] SCK[3]# M
AD
VCCSM
VSS
VSS
SCK[1]
SCS[3]# SCAS#
VSS
SCS[2]# SRAS#
VSS
SMA[10] SMA[0]
VSS
RCVENI RCVEN N# OUT
VSS
SMA[5] SMAB[2]
VSS
SCKE[3] SCKE[2]
VSS
SCKE[0] SMA[8]
SMA[9]
VSS
SCK[2]
SCK[3]
VCCSM
AC
VTTLF
HA[31]# HA[29]#
VSS
SCK[1]# SCK[4]#
SCK[4]
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM SCKE[1] VCCSM SMA[12] SCK[5]# VCCSM
SCK[0]
SMRCO MP
AB
VSS
HADSTB HA[27]# HA[22]# [1]#
VSS
VSS
VSS
RSVD
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCSM
VSS
VCCSM
VSS
NC
VCCSM
VSS
VCCSM
RSVD
VSS
SCK[5]
SCK[0]#
VSS
AA
VTTLF
HCCVRE HA[26]# HA[30]# HA[21]# HA[17]# DPSLP# HAVREF F
VSS
VCCSM
VSS
VCCSM
VSS
VSS
VCCSM GCLKIN
VCCAGP VCCHL LL
Y
VSS
HA[28]# HA[25]#
VSS
HA[20]# HA[23]# HA[24]#
VSS
VCC
VSS
VCCHL
HL[7]
HL[5]
VCCHL
VSS
HLSTB
HL[4]
HLVREF
W
VTTHF
HA[11]# HA[14]# HA[16]# HA[18]#
VSS
HA[19]#
VTTLF
VSS
VCCHL
VSS
VCCHL
HL[6]
HL[9]
HL[10]
HL[3]
HLSTB# VCCHL
V
VSS
HA[10]# HA[12]#
VSS
HA[15]#
HA[8]#
HA[7]#
VSS
VTTLF
VSS
VCC
VSS
VCC
VSS
VSS
VCCHL
HL[0]
VCCHL
VSS
HL[1]
HL[2]
PSWING
VSS
U
HA[5]#
HA[13]#
HADSTB HA[4]# [0]#
VSS
HREQ[4] VTTLF #
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
GAD[15] GAD[0]
GAD[1]
VSS
HL[8]
HLRCO MP
T
HREQ[0] HA[6]# #
VSS
HREQ[3] HREQ[2] HA[9]# # # HREQ[1] #
VSS
VTTLF
VSS
VCC
VSS
VCC
VSS
VSS
VCCDV O
VSS
GAD[5]
GAD[2]
GAD[4]
GAD[3]
VSS
R
BPRI#
HLOCK# RS[1]#
VSS
HA[3]#
VTTLF
VSS
VCC
VSS
VCC
VSS
VCC
VCCDV O
VSS
GSTOP# GAD[7]
GAD[6]
GADSTB GADSTB GCBE#[0 #[0] [0] ] VCCDV O
P
VSS
HITM#
HIT#
VSS
BNR#
DRDY#
RS[0]#
VSS
VTTLF
VSS
VCC
VSS
VCC
VSS
VSS
GDEVSE VCCDV GTRDY# GAD[8] O L#
VSS
GAD[9] GAD[10]
N
VTTHF DEFER# RS[2]#
DBSY# HTRDY#
VSS
BREQ0# VTTLF
VSS
VCCDV VCCDV O O VCCDV O
VSS
VCCDV GFRAM GAD[13] GAD[14] GAD[12] GAD[11] O E# GCBE#[2 GCBE#[1 GAD[16] GAD[18] ] ]
M
VSS
ADS#
HD[6]#
VSS
HD[8]#
HD[3]#
HD[7]#
VSS
VTTLF
VSS
GPAR
VSS
VSS
L
VTTLF
HYSWIN HDSTBP HD[13]# G [0]# HDSTBN HD[4]# [0]#
HD[2]#
VSS
HD[11]#
HD[0]#
HDVREF [0] HDVREF [1] HDVREF [2] VCCDLV DS
VCCDV O
VSS
GIRDY# GAD[17] GAD[19]
VSS
GAD[21] GAD[22] GAD[20]
K
VSS
VSS
DINV[0]# HD[9]#
HD[14]#
VSS
VSS
VTTLF
VSS
VSS
VCC
VSS
VSS
PWROK
VSS
RSVD
VCCDV O
VSS
GAD[23]
GCBE#[3 VCCDV GADSTB GADSTB VCCDV ] O [1] #[1] O
J
HYRCO VTTHF MP
HD[1]#
HD[15]# HD[10]#
VSS
HD[19]#
VTTLF
VSS
VTTLF
VSS
VTTLF
VSS
VTTLF
VSS
VCC
VSS
RSVD
VSS
RSVD
LCLKCT LA
VSS
VCCDV GAD[29] GAD[31] GAD[26] GAD[27] GAD[25] GAD[24] O
H
VSS
HD[5]#
HD[12]#
VSS
HD[21]# HD[24]# HD[30]# HD[27]# HD[33]# HD[40]# DINV[3]# HD[48]# HD[51]# HD[58]#
VTTLF
RSVD
VCCDLV DS
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
GSBA[6] GSBA[4]
VSS
GAD[28] GAD[30]
VSS
G
VTTLF
HD[22]#
VSS
HD[17]# HD[16]#
VSS
HD[44]#
VSS
HD[45]#
VSS
HD[53]#
VSS
HD[56]#
VSS
CPURST #
RSVD
VSS
RSVD
VSS
RSVD
VCCTXL VDS
RSVD
GSBSTB AGPBUS GSBA[7] GSBA[1] GSBA[5] GSBSTB GVREF Y# # VCCDV VCCDV VCCDV GSBA[0] GSBA[2] GSBA[3] O O O EXTTS_ GPIPE# 0 LCLKCT LB DVORC OMP
F
VSS
VSS
HDSTBN HDSTBP HDSTBP HD[20]# HD[29]# DINV[1]# HD[38]# HD[41]# HD[50]# HD[49]# HD[61]# HD[59]# [2]# [2]# [3]# HDSTBP [1]# HDSTBN [3]#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
REFSET
VSS
E
VCCAHP LL
VSS
HD[23]#
VSS
HD[39]#
VSS
HD[36]#
VSS
HD[52]#
VSS
VSS
HD[62]#
VSS
RSVD
VSS
RSVD
VSS
VCCTXL VDS
RSVD
RSVD
RSVD
VSS
GRBF# GWBF#
D
VSS
HD[25]#
HDSTBN HD[28]# HD[37]# HD[34]# HD[35]# [1]#
VSS
HD[47]# HD[46]# HD[54]# HD[63]# HD[55]# HD[60]#
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
RSVD
RSVD
VSS
RSVD
GST[0]
GST[1]
GST[2]
VSS
C
NC
HD[31]# HD[18]# HD[26]# DINV[2]#
VSS
HXSWIN DREFSS VCCADP VCCDLV VCCDLV HXRCO HD[57]# HD[43]# HD[42]# HD[32]# G CLK LLB DS DS MP
RSVD
RSVD
VSSALV VCCTXL VCCADA VSSADA DREFCL DS VDS C C K VCCADA RSVD C
RSVD
VSS
RSVD
GREQ# GGNT#
NC
B
NC
NC
VSS
VTTLF
VSS
VTTHF
VSS
VTTHF
VSS
VTTLF
VSS
VTTLF
VSS
VSS
VCCTXL VCCALV VDS DS
LIBG
RSVD
VCCADP RSVD LLA
VCCGPI VCCGPI O O
NC
A
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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Table 62. Intel(R) 852PM MCH Ballout Table
Row Column E F E E G F G F L F AE AD C D N P M F M B G B C M J E B G D Y N B B 5 5 3 2 5 4 6 6 28 7 29 29 9 9 25 28 23 15 26 6 9 4 5 28 25 25 25 19 5 23 24 7 17 Signal Name ADDID[0] ADDID[1] ADDID[2] ADDID[3] ADDID[4] ADDID[5] ADDID[6] ADDID[7] ADS# AGPBUSY# BCLK BCLK# BLUE BLUE# BNR# BPRI# BREQ0# CPURST# DBSY# DDCACLK DDCADATA DDCPCLK DDCPDATA DEFER# DINV[0]# DINV[1]# DINV[2]# DINV[3]# DPMS DPSLP# DRDY# DREFCLK DREFSSCLK Row Column L M G P P R R M M R R P P N P N N M T T L D D Y C D F U V U T V U 2 3 2 3 4 3 5 1 5 6 4 6 5 5 2 2 3 2 6 5 7 1 6 3 8 8 1 28 28 27 27 27 25 Signal Name DVOBBLANK# DVOBCCLKINT DVOBCINTR# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DVODETECT DVORCOMP EXTTS_0 GCLKIN GREEN GREEN# GVREF HA[10]# HA[11]# HA[12]# HA[13]# HA[14]# HA[15]#
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Row Column V Y V V W Y AA W W W Y AA W AB P Y AB T T R U U R T AA Y Y K H H K G K J H 26 24 25 23 25 25 27 24 23 27 27 28 28 27 23 26 28 25 28 27 23 24 24 26 26 22 28 22 27 25 23 27 26 23 26
Signal Name HA[16]# HA[17]# HA[18]# HA[19]# HA[20]# HA[21]# HA[22]# HA[23]# HA[24]# HA[25]# HA[26]# HA[27]# HA[28]# HA[29]# HA[3]# HA[30]# HA[31]# HA[4]# HA[5]# HA[6]# HA[7]# HA[8]# HA[9]# HADSTB[0]# HADSTB[1]# HAVREF HCCVREF HD[0]# HD[1]# HD[10]# HD[11]# HD[12]# HD[13]# HD[14]# HD[15]#
Row Column F F B H K E G F D G C B G C E L G B B G C C D C E D J G E B B F F C C 25 26 27 23 25 27 25 28 27 24 28 26 22 26 26 24 23 28 21 21 24 23 22 25 24 24 27 20 23 22 23 23 21 20 21
Signal Name HD[16]# HD[17]# HD[18]# HD[19]# HD[2]# HD[20]# HD[21]# HD[22]# HD[23]# HD[24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]# HD[3]# HD[30]# HD[31]# HD[32]# HD[33]# HD[34]# HD[35]# HD[36]# HD[37]# HD[38]# HD[39]# HD[4]# HD[40]# HD[41]# HD[42]# HD[43]# HD[44]# HD[45]# HD[46]# HD[47]#
262
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Row Column G E G E G D F C C F B G E L C E D C L L J J C E D K D E E K J J N N U 18 19 28 20 17 20 19 19 17 17 19 16 16 27 16 17 16 18 23 25 24 28 27 22 18 27 26 21 18 21 21 17 27 28 7
Signal Name HD[48]# HD[49]# HD[5]# HD[50]# HD[51]# HD[52]# HD[53]# HD[54]# HD[55]# HD[56]# HD[57]# HD[58]# HD[59]# HD[6]# HD[60]# HD[61]# HD[62]# HD[63]# HD[7]# HD[8]# HD[9]# HDSTBN[0]# HDSTBN[1]# HDSTBN[2]# HDSTBN[3]# HDSTBP[0]# HDSTBP[1]# HDSTBP[2]# HDSTBP[3]# HDVREF[0] HDVREF[1] HDVREF[2] HIT# HITM# HL[0]
Row Column U V U V W W V W T V P T W V W R P R R T H M B B H K D E E F G E C C F 4 4 3 3 2 6 6 7 3 5 27 2 3 2 1 28 25 23 25 23 10 25 20 18 28 28 14 13 10 10 14 15 15 13 14
Signal Name HL[1] HL[10] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HLOCK# HLRCOMP HLSTB HLSTB# HLVREF HREQ[0]# HREQ[1]# HREQ[2]# HREQ[3]# HREQ[4]# HSYNC HTRDY# HXRCOMP HXSWING HYRCOMP HYSWING ICLKAM ICLKAP ICLKBM ICLKBP IYAM[0] IYAM[1] IYAM[2] IYAM[3] IYAP[0]
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Row Column E C B H E C G G E C G H C A P T N M K N AJ AH B A AJ A AA AJ AJ A AH B G F A 14 14 13 12 12 12 11 12 11 11 10 9 6 10 7 7 7 6 7 6 29 29 29 29 28 28 9 4 2 2 1 1 8 8 5
Signal Name IYAP[1] IYAP[2] IYAP[3] IYBM[0] IYBM[1] IYBM[2] IYBM[3] IYBP[0] IYBP[1] IYBP[2] IYBP[3] LCLKCTLA LCLKCTLB LIBG MDDCCLK MDDCDATA MDVICLK MDVIDATA MI2CCLK MI2CDATA NC NC NC NC NC NC NC NC NC NC NC NC PANELBKLTCTL PANELBKLTEN PANELVDDEN
Row Column U J AC AC A A E N P M AD AA L J J K K H G K K J J H H H H H K L F D B AA L 2 11 16 15 7 8 8 23 26 27 28 22 3 3 2 5 1 6 3 3 2 6 5 2 1 3 4 5 6 5 12 12 12 5 4
Signal Name PSWING PWROK RCVENIN# RCVENOUT RED RED# REFSET RS[0]# RS[1]# RS[2]# RSTIN# RSVD DVOCBLANK# DVOCCLK DVOCCLK# DVOCD[0] DVOCD[1] DVOCD[10] DVOCD[11] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6] DVOCD[7] DVOCD[8] DVOCD[9] DVOCFLDSTL DVOCHSYNC DVOCVSYNC RSVD RSVD RSVD RSVD RSVD
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Row Column C F D C B F D C B D AD AD AC AB AA AC AB AC AD AC AD AB AB AA AB AC AB AC AC AD AD AC AC AE AE 4 3 3 3 3 2 2 2 2 7 22 20 24 2 2 26 25 3 4 2 2 23 24 3 4 7 7 9 10 23 26 22 25 5 6
Signal Name GST[0] RSVD RSVD GST[1] RSVD RSVD RSVD RSVD RSVD RSVD SBA[0] SBA[1] SCAS# SCK[0] SCK[0]# SCK[1] SCK[1]# SCK[2] SCK[2]# SCK[3] SCK[3]# SCK[4] SCK[4]# SCK[5] SCK[5]# SCKE[0] SCKE[1] SCKE[2] SCKE[3] SCS[0]# SCS[1]# SCS[2]# SCS[3]# SDM[0] SDM[1]
Row Column AE AH AD AD AD AH AH AF AE AG AE AF AH AF AH AF AG AH AG AF AH AD AF AE AH AH AG AF AG AD AH AF AH AH AG 9 12 19 21 24 28 15 2 3 7 8 5 4 7 6 8 8 9 10 4 7 9 10 11 10 11 13 14 11 12 2 13 13 16 17
Signal Name SDM[2] SDM[3] SDM[4] SDM[5] SDM[6] SDM[7] SDM[8] SDQ[0] SDQ[1] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17] SDQ[18] SDQ[19] SDQ[2] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[3] SDQ[30] SDQ[31] SDQ[32] SDQ[33]
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Row Column AF AE AD AE AH AG AD AH AG AF AH AF AH AH AG AE AH AE AE AH AG AF AF AG AH AE AG AF AG AG AF AE AD AG AE 19 20 18 18 18 19 3 20 20 22 22 20 19 21 22 23 23 2 24 25 23 23 25 25 26 26 28 28 4 26 26 27 27 14 14
Signal Name SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[4] SDQ[40] SDQ[41] SDQ[42] SDQ[43] SDQ[44] SDQ[45] SDQ[46] SDQ[47] SDQ[48] SDQ[49] SDQ[5] SDQ[50] SDQ[51] SDQ[52] SDQ[53] SDQ[54] SDQ[55] SDQ[56] SDQ[57] SDQ[58] SDQ[59] SDQ[6] SDQ[60] SDQ[61] SDQ[62] SDQ[63] SDQ[64] SDQ[65]
Row Column AE AG AH AE AH AF AF AD AG AG AH AH AE AH AE AH AH AD AC AD AC AD AB AD AD AD AC AD AD AC AC AD AC AF AD 17 16 14 15 3 16 17 6 5 2 5 8 12 17 21 24 27 15 18 14 19 5 5 13 17 11 13 8 7 6 5 16 12 11 10
Signal Name SDQ[66] SDQ[67] SDQ[68] SDQ[69] SDQ[7] SDQ[70] SDQ[71] SDQ[8] SDQ[9] SDQS[0] SDQS[1] SDQS[2] SDQS[3] SDQS[4] SDQS[5] SDQS[6] SDQS[7] SDQS[8] SMA[0] SMA[1] SMA[10] SMA[11] SMA[12] SMA[2] SMA[3] SMA[4] SMA[5] SMA[6] SMA[7] SMA[8] SMA[9] SMAB[1] SMAB[2] SMAB[4] SMAB[5]
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Row Column AB AJ AJ AJ AC AD W AA AA T P U R N AA T P J U R N H T P B A A B Y D A AF AD B B 1 24 19 22 21 25 21 19 17 17 17 16 16 16 15 15 15 15 14 14 14 14 13 13 9 9 6 16 2 29 11 1 1 15 14
Signal Name SMRCOMP SMVREF_0 SMVSWINGH SMVSWINGL SRAS# SWE# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCADAC VCCADAC VCCADPLLA VCCADPLLB VCCAGPLL VCCAHPLL VCCALVDS VCCASM VCCASM VCCDLVDS VCCDLVDS
Row Column J G P M K R N M L J H E M J E N J E A A V W U V U W Y V AJ AJ AG AF AC AF AJ 13 13 9 9 9 8 8 8 8 8 7 6 4 4 4 1 1 1 4 3 9 8 8 7 6 5 1 1 8 6 29 29 29 27 25
Signal Name VCCDLVDS VCCDLVDS VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCGPIO VCCGPIO VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCQSM VCCQSM VCCSM VCCSM VCCSM VCCSM VCCSM
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Row Column AF AB AJ AF AB AF AB AJ AB AF AB AJ AA AF AB AA AB AJ AF Y AB AA Y AF AB AA AJ Y AF AB AG AC A D B 24 22 21 21 20 18 18 17 16 15 14 13 13 12 12 11 10 9 9 9 8 8 7 6 6 6 5 4 3 3 1 1 12 10 10
Signal Name VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCTXLVDS VCCTXLVDS VCCTXLVDS
Row Column F AA W U N L J G E C AE AC E D AJ AG AC F A AJ AB W U R N L J G AE AA D A AG AA V 9 29 29 29 29 29 29 29 29 29 28 28 28 28 27 27 27 27 27 26 26 26 26 26 26 26 26 26 25 25 25 25 24 24 24
Signal Name VCCTXLVDS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column T P M K H F B AJ AC AA D A AE W U R N L J F C AG AB AA Y V T P M H D A AJ AC AA 24 24 24 24 24 24 24 23 23 23 23 23 22 22 22 22 22 22 22 22 22 21 21 21 21 21 21 21 21 21 21 21 20 20 20
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column J F AE AB H D A AJ AG AA J F AC AB U R N H D A AE AA T P J F AG AB U R N H D AC AA 20 20 19 19 19 19 19 18 18 18 18 18 17 17 17 17 17 17 17 17 16 16 16 16 16 16 15 15 15 15 15 15 15 14 14
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column T P J AE AB U R N H F D A AJ AG AA J AJ AC AB H F D AJ AE AA J C AG AB W U T R N L 14 14 14 13 13 13 13 13 13 13 13 13 12 12 12 12 11 11 11 11 11 11 10 10 10 10 10 9 9 9 9 9 9 9 9
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column E AC Y V T P K H AJ AE AA R M J G E C AG Y L Y U B AE AC AA W T N K G D AJ AG R 9 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 6 6 6 5 5 5 4 4 4 4 4 4 4 4 4 3 3 2
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column AJ AE AA U L G C B B J V M H A A AB Y K F A V T P M H P P R R M M R R P P 1 1 1 1 1 1 1 8 11 9 29 29 29 24 22 29 29 29 29 26 22 22 22 22 22 3 4 3 5 1 5 6 4 6 5
Signal Name VSS VSS VSS VSS VSS VSS VSS VSSADAC VSSALVDS VSYNC VTTHF VTTHF VTTHF VTTHF VTTHF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF VTTLF RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Row Column N P N N M T T L D D Y C D F U V U T V U V Y V V W E G F D G C B G C E 5 2 2 3 2 6 5 7 1 6 3 8 8 1 28 28 27 27 27 25 26 24 25 23 25 27 25 28 27 24 28 26 22 26 26
Signal Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD DVODETECT DVORCOMP EXTTS_0 GCLKIN GREEN GREEN# GVREF HA[10]# HA[11]# HA[12]# HA[13]# HA[14]# HA[15]# HA[16]# HA[17]# HA[18]# HA[19]# HA[20]# HD[20]# HD[21]# HD[22]# HD[23]# HD[24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]#
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Row Column L G B B G C C D C E D J G E B B F F C C G E G E G V W T V P T W V W R 24 23 28 21 21 24 23 22 25 24 24 27 20 23 22 23 23 21 20 21 18 19 28 20 17 6 7 3 5 27 2 3 2 1 28
Signal Name HD[3]# HD[30]# HD[31]# HD[32]# HD[33]# HD[34]# HD[35]# HD[36]# HD[37]# HD[38]# HD[39]# HD[4]# HD[40]# HD[41]# HD[42]# HD[43]# HD[44]# HD[45]# HD[46]# HD[47]# HD[48]# HD[49]# HD[5]# HD[50]# HD[51]# HL[6] HL[7] HL[8] HL[9] HLOCK# HLRCOMP HLSTB HLSTB# HLVREF HREQ[0]#
Row Column P R R T H M B B H K D E E F G E C C F E C B H E C G N P M AD AA L J J K 25 23 25 23 10 25 20 18 28 28 14 13 10 10 14 15 15 13 14 14 14 13 12 12 12 11 23 26 27 28 22 3 3 2 5
Signal Name HREQ[1]# HREQ[2]# HREQ[3]# HREQ[4]# HSYNC HTRDY# HXRCOMP HXSWING HYRCOMP HYSWING ICLKAM ICLKAP ICLKBM ICLKBP IYAM[0] IYAM[1] IYAM[2] IYAM[3] IYAP[0] IYAP[1] IYAP[2] IYAP[3] IYBM[0] IYBM[1] IYBM[2] IYBM[3] RS[0]# RS[1]# RS[2]# RSTIN# RSVD DVOCBLANK# DVOCCLK DVOCCLK# DVOCD[0]
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Row Column K H G K K J J H H H H H K L F D B AA L C F D C B F D AE AG AE AF AH AF AH AF AG 1 6 3 3 2 6 5 2 1 3 4 5 6 5 12 12 12 5 4 4 3 3 3 3 2 2 3 7 8 5 4 7 6 8 8
Signal Name DVOCD[1] DVOCD[10] DVOCD[11] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6] DVOCD[7] DVOCD[8] DVOCD[9] DVOCFLDSTL DVOCHSYNC DVOCVSYNC RSVD RSVD RSVD RSVD RSVD GST[0] RSVD RSVD GST[1] RSVD RSVD RSVD SDQ[1] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17]
Row Column AH AG AF AH AD AF AE AH AH AG AF AG AD AH AF AH AH AG AF AE AD AE AH AG AD AH AG AE AG AE AF AH AF AH AF 9 10 4 7 9 10 11 10 11 13 14 11 12 2 13 13 16 17 19 20 18 18 18 19 3 20 20 3 7 8 5 4 7 6 8
Signal Name SDQ[18] SDQ[19] SDQ[2] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[3] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[4] SDQ[40] SDQ[41] SDQ[1] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16]
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Row Column AG AH AG AF AH AD AF AE AH AH AG AF AG AD AH AF AH AH AG AF AE AD AE AH AG AD AH AG AG AH AH AE AH AE AH 8 9 10 4 7 9 10 11 10 11 13 14 11 12 2 13 13 16 17 19 20 18 18 18 19 3 20 20 2 5 8 12 17 21 24
Signal Name SDQ[17] SDQ[18] SDQ[19] SDQ[2] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[3] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[4] SDQ[40] SDQ[41] SDQS[0] SDQS[1] SDQS[2] SDQS[3] SDQS[4] SDQS[5] SDQS[6]
Row Column AH AD AC AD AC AD AB AD AD AD AC AD AD AC AC AD AC AF AD AB AJ AJ AJ AC AD W AA AA H E M J E N J 27 15 18 14 19 5 5 13 17 11 13 8 7 6 5 16 12 11 10 1 24 19 22 21 25 21 19 17 7 6 4 4 4 1 1
Signal Name SDQS[7] SDQS[8] SMA[0] SMA[1] SMA[10] SMA[11] SMA[12] SMA[2] SMA[3] SMA[4] SMA[5] SMA[6] SMA[7] SMA[8] SMA[9] SMAB[1] SMAB[2] SMAB[4] SMAB[5] SMRCOMP SMVREF_0 SMVSWINGH SMVSWINGL SRAS# SWE# VCC VCC VCC VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO VCCDVO
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Row Column E A A V W U V U W Y V AJ AJ AG AF AC AF AJ AF AB AJ AF AB AF AB AJ AB AF AB AC E D AJ AG AC 1 4 3 9 8 8 7 6 5 1 1 8 6 29 29 29 27 25 24 22 21 21 20 18 18 17 16 15 14 28 28 28 27 27 27
Signal Name VCCDVO VCCGPIO VCCGPIO VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCHL VCCQSM VCCQSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VSS VSS VSS VSS VSS VSS
Row Column F A AJ AB W U R N L J G AE AA D A AG AA V T P M K H F B AJ AC AA D AC AB U R N H 27 27 26 26 26 26 26 26 26 26 26 25 25 25 25 24 24 24 24 24 24 24 24 24 24 23 23 23 23 17 17 17 17 17 17
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Row Column D A AE AA T P J F AG AB U R N H D AC AA T P J AE AB U R N H F D A AJ J G E C AG 17 17 16 16 16 16 16 16 15 15 15 15 15 15 15 14 14 14 14 14 13 13 13 13 13 13 13 13 13 12 7 7 7 7 6
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Row Column Y L Y U B AE AC AA W T N K G D AJ AG R AJ AE AA U L G C B B J V M H U R N L H 6 6 5 5 5 4 4 4 4 4 4 4 4 4 3 3 2 1 1 1 1 1 1 1 8 11 9 29 29 29 21 21 21 21 20
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSADAC VSSALVDS VSYNC VTTHF VTTHF VTTHF VTTLF VTTLF VTTLF VTTLF VTTLF
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Row Column A J H 20 19 18
Signal Name VTTLF VTTLF VTTLF
Row Column A H G 18 16 15
Signal Name VTTLF VTTLF VTTLF
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9.1
Package Mechanical Information
The following figures provide details on the package information and dimensions of the Intel(R) 852GME GMCH and Intel 852PM MCH chipsets. The GMCH/MCH comes in a Micro-FCBGA package similar to the mobile processors. The package consists of a silicon die mounted face down on an organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding the die. Because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the capacitors and possibly damage the device or render it inactive. The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. An exclusion, or keepout area, surrounds the die and capacitors, and identifies the contact area for the package. Care should be taken to avoid contact with the package inside this area.
Figure 16. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Micro-FCBGA Package Dimensions (Top View)
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Figure 17. Intel(R) 852GME GMCH and Intel(R) 852PM MCH Micro-FCBGA Package Dimensions (Side View)
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